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1. 发明授权

US07685493B2 Buffer compression in automatic retransmission request (ARQ) systems 有权
标题翻译：自动重传请求（ARQ）系统中的缓冲区压缩
公开(公告)号：US07685493B2
公开(公告)日：2010-03-23
申请号：US11540794
申请日：2006-09-29
申请人： Benjamin John Widdup , Koen van den Beld
发明人： Benjamin John Widdup , Koen van den Beld
IPC分类号： H04L1/16
CPC分类号： H04L1/1845 , H04L1/1835
摘要： A method and system for improving buffer compression in automatic retransmission request (ARQ) systems includes both a compander and decompander for further processing data. A received data string k bits in length is first companded according to a predetermined companding scheme. The companded data string is reduced to a length of k−1 bits for more efficient storage. Upon receipt of a request for retransmission, the stored companded data string is loaded and decompanded back to a length of k bits. Once decompanded, the data string is combined with a retransmitted data string to produce a single data string with an increased likelihood of being correct. By companding the data string before storage, a smaller memory block can be used for the storage of the data string.
摘要翻译：在自动重发请求（ARQ）系统中改进缓冲器压缩的方法和系统包括用于进一步处理数据的压缩扩展器和分解缓冲器。首先按照预定的压缩方案压缩接收到的长度为k位的数据串。压缩的数据串被减少到k-1位的长度以便更有效地存储。在接收到重传请求时，将所存储的压缩数据串加载并解压缩到k比特的长度。一旦解压缩，数据串与重新发送的数据串组合，以产生具有增加的正确可能性的单个数据串。通过在存储之前压缩数据串，可以使用较小的内存块来存储数据串。

2. 发明申请

US20080092008A1 Buffer compression in automatic retransmisson request (ARQ) systems 有权
标题翻译：自动重传密码请求（ARQ）系统中的缓冲区压缩
公开(公告)号：US20080092008A1
公开(公告)日：2008-04-17
申请号：US11540794
申请日：2006-09-29
申请人： Benjamin John Widdup , Koen van den Beld
发明人： Benjamin John Widdup , Koen van den Beld
IPC分类号： H04L1/18
CPC分类号： H04L1/1845 , H04L1/1835
摘要： A method and system for improving buffer compression in automatic retransmission request (ARQ) systems includes both a compander and decompander for further processing data. A received data string k bits in length is first companded according to a predetermined companding scheme. The companded data string is reduced to a length of k−1 bits for more efficient storage. Upon receipt of a request for retransmission, the stored companded data string is loaded and decompanded back to a length of k bits. Once decompanded, the data string is combined with a retransmitted data string to produce a single data string with an increased likelihood of being correct. By companding the data string before storage, a smaller memory block can be used for the storage of the data string.
摘要翻译：在自动重发请求（ARQ）系统中改进缓冲器压缩的方法和系统包括用于进一步处理数据的压缩扩展器和分解缓冲器。首先按照预定的压缩方案压缩接收到的长度为k位的数据串。压缩的数据串被减少到k-1位的长度以便更有效地存储。在接收到重传请求时，将所存储的压缩数据串加载并解压缩到k比特的长度。一旦解压缩，数据串与重新发送的数据串组合，以产生具有增加的正确可能性的单个数据串。通过在存储之前压缩数据串，可以使用较小的内存块来存储数据串。

3. 发明授权

US08196006B2 Modified branch metric calculator to reduce interleaver memory and improve performance in a fixed-point turbo decoder 失效
标题翻译：改进的分支度量计算器，以减少交织器存储器并提高定点turbo解码器的性能
公开(公告)号：US08196006B2
公开(公告)日：2012-06-05
申请号：US12323558
申请日：2008-11-26
申请人： Mark Andrew Bickerstaff , Benjamin John Widdup
发明人： Mark Andrew Bickerstaff , Benjamin John Widdup
IPC分类号： H03M13/00
CPC分类号： H03M13/2957 , H03M13/2771 , H03M13/3927
摘要： A turbo decoder that calculates alpha, beta and gamma (branch metric) values does not normalize the branch metric but instead applies the normalization factor to the newly calculated extrinsic values before writing them to interleaving memory, resulting in use of less memory than in prior turbo decoders. A compensating factor is applied when the extrinsics are read from interleaving memory. The absence of normalization in the gamma calculation not only conserves memory but also enhances decoder sensitivity.
摘要翻译：计算α，β和γ（分支度量）值的turbo解码器不会使分支度量标准化，而是在将它们写入交织存储器之前将归一化因子应用于新计算的外在值，导致使用比现有涡轮机更少的存储器解码器当从交织存储器中读取二进制时，应用补偿因子。伽马计算中不存在归一化不仅节约了存储器，而且增强了解码器的灵敏度。

4. 发明授权

US07500167B2 BER calculation device for calculating the BER during the decoding of an input signal 有权
标题翻译： BER计算装置，用于在输入信号的解码期间计算BER
公开(公告)号：US07500167B2
公开(公告)日：2009-03-03
申请号：US10259303
申请日：2002-09-30
申请人： Benjamin John Widdup
发明人： Benjamin John Widdup
IPC分类号： H03M13/00
CPC分类号： H03M13/612 , H03M13/2714 , H03M13/2948 , H03M13/2957 , H03M13/37
摘要： In a decoder, the BER is calculated during a decode operation of the decoder. Access to decoder components for obtaining signal data for use in calculating the BER is provided during the decode operation when the components are not used by the decoder. A fetch component serves to provide the input signal to both the decoder and BER calculator at the same time. The BER calculator calculates the BER based on the output from the previous iteration. Since the decoder keep decoding the data until the final two iterations result in the same output, the calculation of the BER can be performed during the last iteration of the decoding process. An HDA early termination signal is used to confirm an accurate BER calculation.
摘要翻译：在解码器中，在解码器的解码操作期间计算BER。当解码器不使用组件时，在解码操作期间提供对用于获得用于计算BER的信号数据的解码器组件的访问。提取组件用于同时向解码器和BER计算器提供输入信号。 BER计算器根据前一次迭代的输出计算BER。由于解码器保持对数据进行解码，直到最后的两次迭代产生相同的输出，所以可以在解码过程的最后一次迭代期间执行BER的计算。 HDA提前终止信号用于确认精确的BER计算。

5. 发明授权

US06651148B2 High-speed memory controller for pipelining memory read transactions 有权
标题翻译：用于流水线存储器读取事务的高速存储器控制器
公开(公告)号：US06651148B2
公开(公告)日：2003-11-18
申请号：US09861576
申请日：2001-05-22
申请人： Benjamin John Widdup
发明人： Benjamin John Widdup
IPC分类号： G06F1300
CPC分类号： G06F13/1605
摘要： A memory controller (218) is disclosed which includes a write arbiter (130) and a read arbiter (140) for receiving and processing memory requests from a number of requestor modules (190) for accessing a high speed memory device (110). A high speed controller (120) controls data flow to and from the high speed memory device (110) at a frequency that is higher than ail operating of the arbiters (130, 140), allowing pseudo-simultaneous memory transactions. A read data dispatcher (160) is also disclosed for receiving data from the high speed controller (120) in response to read transactions and for passing the data to one of the requestor modules (190). The size and destination information for launched read transactions are kept by a queue 150. When return data is received by the read data dispatcher (160), the read data dispatcher (160) matches the appropriate amount of data with each queue entry and delivers that return data to the appropriate requester module (190).
摘要翻译：公开了一种存储器控制器（218），其包括写仲裁器（130）和读仲裁器（140），用于接收和处理来自用于访问高速存储器设备（110）的多个请求器模块（190）的存储器请求。高速控制器（120）以高于仲裁器（130,140）的操作的频率来控制来往高速存储器件（110）的数据流，从而允许伪同时存储器事务。还公开了一种读取数据调度器（160），用于响应于读取事务从高速控制器（120）接收数据并将数据传送到请求者模块（190）之一。用于启动的读事务的大小和目的地信息由队列150保存。当读数据调度器（160）接收到返回数据时，读数据调度器（160）将适当数量的数据与每个队列条目进行匹配，将数据返回给相应的请求者模块（190）。

6. 发明授权

US07607065B2 Method and apparatus for block and rate independent decoding of LDPC codes 失效
标题翻译：用于LDPC码的块和速率独立解码的方法和装置
公开(公告)号：US07607065B2
公开(公告)日：2009-10-20
申请号：US11191158
申请日：2005-07-27
申请人： Mark Andrew Bickerstaff , Graeme Edwin Pope , Benjamin John Widdup , Graeme Kenneth Woodward
发明人： Mark Andrew Bickerstaff , Graeme Edwin Pope , Benjamin John Widdup , Graeme Kenneth Woodward
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1111 , H03M13/6516
摘要： Methods and apparatus are provided for block and rate independent decoding of LDPC codes. The disclosed LDPC decoders support multiple code block lengths and code rates, as well as a variable parity check matrix. The disclosed LDPC decoders decode LDPC codes that are based on a parity check matrix having a plurality of sub-matrices, wherein each row and column of the plurality of sub-matrices has a single entry. Each of the sub-matrices has at least one associated Phi-node, wherein each Phi-node comprises a memory device having a plurality of memory elements, wherein one or more of the memory elements may be selectively disabled. The Phi-nodes may be selectively disabled, for example, at run-time. The Phi-node optionally further comprises a multiplexer in order to provide a variable parity check matrix.
摘要翻译：提供了用于LDPC码的块速率独立解码的方法和装置。所公开的LDPC解码器支持多个码块长度和码率，以及可变奇偶校验矩阵。所公开的LDPC解码器对基于具有多个子矩阵的奇偶校验矩阵的LDPC码进行解码，其中多个子矩阵中的每一行和列具有单个条目。每个子矩阵具有至少一个相关联的Phi节点，其中每个Phi节点包括具有多个存储器元件的存储器件，其中一个或多个存储器元件可被选择性地禁用。 Phi节点可以被选择性地禁用，例如在运行时。 Phi节点可选地还包括多路复用器以提供可变奇偶校验矩阵。

7. 发明授权

US07590917B2 Parameter generation for interleavers 有权
标题翻译：交织器的参数生成
公开(公告)号：US07590917B2
公开(公告)日：2009-09-15
申请号：US10427833
申请日：2003-05-01
申请人： Mark Patrick Barry , Benjamin John Widdup
发明人： Mark Patrick Barry , Benjamin John Widdup
IPC分类号： H03M13/00
CPC分类号： H03M13/2764 , H03M13/2725 , H03M13/276 , H03M13/2957 , H03M13/6561
摘要： An interleaver parameter generator circuit used to calculate and generate on an as needed basis interleaver parameters for interleaving blocks of information of varying lengths in accordance with a pseudorandom pattern defined by the 3GPP standard. The interleaver parameter generator circuit calculates and generates the defined interleaver parameters based on an input parameter that represents the length of the block of information to be interleaved. At least one of the defined parameters is calculated and generated using a decomposed form of its definition. The interleaver parameter generator circuit uses well known circuit blocks such as multipliers, subtractors, Compare-and-Select circuits and other circuits to calculate and generate the defined parameters.
摘要翻译：交织器参数发生器电路，用于根据由3GPP标准定义的伪随机模式，根据需要基于交织器参数来计算和生成用于交织不同长度的信息块的交织器参数。交织器参数发生器电路基于表示待交织的信息块的长度的输入参数来计算并生成定义的交织器参数。使用其定义的分解形式来计算和生成至少一个定义的参数。交织器参数发生器电路使用众所周知的电路块，例如乘法器，减法器，比较和选择电路和其他电路来计算和生成定义的参数。

8. 发明申请

US20090077330A1 MODIFIED BRANCH METRIC CALCULATOR TO REDUCE INTERLEAVER MEMORY AND IMPROVE PERFORMANCE IN A FIXED-POINT TURBO DECODER 失效
标题翻译：改进的分支计量器来减少交叉存储器并提高固定点涡轮解码器的性能
公开(公告)号：US20090077330A1
公开(公告)日：2009-03-19
申请号：US12323558
申请日：2008-11-26
申请人： Mark Andrew Bickerstaff , Benjamin John Widdup
发明人： Mark Andrew Bickerstaff , Benjamin John Widdup
IPC分类号： G06F12/06
CPC分类号： H03M13/2957 , H03M13/2771 , H03M13/3927
摘要： A turbo decoder that calculates alpha, beta and gamma (branch metric) values does not normalize the branch metric but instead applies the normalization factor to the newly calculated extrinsic values before writing them to interleaving memory, resulting in use of less memory than in prior turbo decoders. A compensating factor is applied when the extrinsics are read from interleaving memory. The absence of normalization in the gamma calculation not only conserves memory but also enhances decoder sensitivity.
摘要翻译：计算α，β和γ（分支度量）值的turbo解码器不会使分支度量标准化，而是在将它们写入交织存储器之前将归一化因子应用于新计算的外在值，导致使用比现有涡轮机更少的存储器解码器当从交织存储器中读取二进制时，应用补偿因子。伽马计算中不存在归一化不仅节约了存储器，而且增强了解码器的灵敏度。

9. 发明授权

US07464316B2 Modified branch metric calculator to reduce interleaver memory and improve performance in a fixed-point turbo decoder 失效
标题翻译：改进的分支度量计算器，以减少交织器存储器并提高定点turbo解码器的性能
公开(公告)号：US07464316B2
公开(公告)日：2008-12-09
申请号：US11212186
申请日：2005-08-26
申请人： Mark Andrew Bickerstaff , Benjamin John Widdup
发明人： Mark Andrew Bickerstaff , Benjamin John Widdup
IPC分类号： H03M13/00
CPC分类号： H03M13/2957 , H03M13/2771 , H03M13/3927
摘要： A turbo decoder that calculates alpha, beta and gamma (branch metric) values does not normalize the branch metric but instead applies the normalization factor to the newly calculated extrinsic values before writing them to interleaving memory, resulting in use of less memory than in prior turbo decoders. A compensating factor is applied when the extrinsics are read from interleaving memory. The absence of normalization in the gamma calculation not only conserves memory but also enhances decoder sensitivity.
摘要翻译：计算α，β和γ（分支度量）值的turbo解码器不会使分支度量标准化，而是在将它们写入交织存储器之前将归一化因子应用于新计算的外在值，导致使用比现有涡轮机更少的存储器解码器当从交织存储器中读取二进制时，应用补偿因子。伽马计算中不存在归一化不仅节约了存储器，而且增强了解码器的灵敏度。

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