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1. 发明授权

US08140903B2 Hardware process trace facility 有权
标题翻译：硬件过程跟踪工具
公开(公告)号：US08140903B2
公开(公告)日：2012-03-20
申请号：US12425075
申请日：2009-04-16
申请人： Benjiman L. Goodman , Sertac Cakici , Samuel I. Ward , Linton B. Ward, Jr.
发明人： Benjiman L. Goodman , Sertac Cakici , Samuel I. Ward , Linton B. Ward, Jr.
IPC分类号： G06F11/00
CPC分类号： G06F11/349 , G06F2201/87
摘要： A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread comprising an ordered series of thread instructions. In the event the first thread instruction is a set bus trace enable bit (BTEB) instruction, the processor sets a bus trace enable bit corresponding to the thread. In the event the BTEB is set, the processor determines whether the first thread instruction is a trace-eligible instruction and, in the event the first thread instruction is a trace-eligible instruction, and the BTEB is set, the processor sets a snoop tag trace enable bit (STTEB). A hardware trace monitor (HTM) monitors bus transactions, each bus transaction comprising a STTE. In the event a monitored bus transaction comprises a set STTEB, the HTM stores the bus transaction as trace data. In the event a monitored bus transaction comprises a reset STTEB, the HTM does not store the bus transaction as trace data.
摘要翻译：用于在多处理器系统中跟踪线程总线事务的方法包括由处理器解码线程的第一线程指令，所述线程包括有序序列的线程指令。在第一个线程指令是一个设置的总线跟踪使能位（BTEB）指令的情况下，处理器设置与线程相对应的总线跟踪使能位。在设置BTEB的情况下，处理器确定第一个线程指令是否是符合条件的指令，并且在第一个线程指令是符合跟踪条件的指令的情况下，并且BTEB被设置，处理器设置一个窥探标记跟踪使能位（STTEB）。硬件跟踪监视器（HTM）监视总线事务，每个总线事务包括STTE。在监控总线事务包括一组STTEB的情况下，HTM将总线事务存储为跟踪数据。在监控总线事务包括复位STTEB的情况下，HTM不将总线事务存储为跟踪数据。

2. 发明授权

US07925948B2 System and method for power reduction through power aware latch weighting 有权
标题翻译：通过功率感知锁存器加权降低功耗的系统和方法
公开(公告)号：US07925948B2
公开(公告)日：2011-04-12
申请号：US12206789
申请日：2008-09-09
申请人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
发明人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
IPC分类号： G01R31/28
CPC分类号： G06F11/263 , G01R31/3183
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.
摘要翻译：一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。不需要的分析模块识别DUT内的绝对不需要的锁存器，为所识别的不可用锁存器的位置分配一个加权值，并在一般测试中识别绝对不需要的位模式。电路分析模块根据相关位位置的加权值替代通用测试模式中识别的绝对不关心位，生成加权测试模式。测试向量模块基于加权测试模式生成测试向量，并且输入模块将测试向量应用于DUT。

3. 发明授权

US07930610B2 System and method for power reduction through power aware latch weighting of complex sub-circuits 有权
标题翻译：通过复杂子电路的功率感知锁存器加权降低功耗的系统和方法
公开(公告)号：US07930610B2
公开(公告)日：2011-04-19
申请号：US12206781
申请日：2008-09-09
申请人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
发明人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.
摘要翻译：一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。电路分析模块分析DUT内的子电路的DUT，并识别所识别的子电路的逻辑描述。不需要的分析模块耦合到电路分析模块，识别与所识别的子电路相关的绝对不需要的锁存器。子电路异常模块耦合到电路分析模块，并且基于所识别的绝对不需要的锁存器和所识别的子电路的逻辑描述来选择所识别的子电路的加权输入值。子电路异常模块存储用于子电路的选择的加权输入值，并将所选择的加权输入值与逻辑描述相关联。

4. 发明授权

US08788864B2 Coordinated approach between middleware application and sub-systems 有权
标题翻译：中间件应用程序和子系统之间的协调方法
公开(公告)号：US08788864B2
公开(公告)日：2014-07-22
申请号：US13271490
申请日：2011-10-12
申请人： Sunil J. Kamath , Bernhard K. Schiefer , Linton B. Ward, Jr.
发明人： Sunil J. Kamath , Bernhard K. Schiefer , Linton B. Ward, Jr.
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： A method of managing power in a computing system is provided. The method comprises: assessing incoming work; assessing service level agreements related to the incoming work; and coordinating with an operating system layer to control hardware of the computing system based on the service level agreements and a power consumption goal.
摘要翻译：提供了一种在计算系统中管理电力的方法。该方法包括：评估传入的工作; 评估与入职工作相关的服务水平协议; 并且与操作系统层协调以基于服务水平协议和功耗目标来控制计算系统的硬件。

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