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1. 发明授权

US08140903B2 Hardware process trace facility 有权
标题翻译：硬件过程跟踪工具
公开(公告)号：US08140903B2
公开(公告)日：2012-03-20
申请号：US12425075
申请日：2009-04-16
申请人： Benjiman L. Goodman , Sertac Cakici , Samuel I. Ward , Linton B. Ward, Jr.
发明人： Benjiman L. Goodman , Sertac Cakici , Samuel I. Ward , Linton B. Ward, Jr.
IPC分类号： G06F11/00
CPC分类号： G06F11/349 , G06F2201/87
摘要： A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread comprising an ordered series of thread instructions. In the event the first thread instruction is a set bus trace enable bit (BTEB) instruction, the processor sets a bus trace enable bit corresponding to the thread. In the event the BTEB is set, the processor determines whether the first thread instruction is a trace-eligible instruction and, in the event the first thread instruction is a trace-eligible instruction, and the BTEB is set, the processor sets a snoop tag trace enable bit (STTEB). A hardware trace monitor (HTM) monitors bus transactions, each bus transaction comprising a STTE. In the event a monitored bus transaction comprises a set STTEB, the HTM stores the bus transaction as trace data. In the event a monitored bus transaction comprises a reset STTEB, the HTM does not store the bus transaction as trace data.
摘要翻译：用于在多处理器系统中跟踪线程总线事务的方法包括由处理器解码线程的第一线程指令，所述线程包括有序序列的线程指令。在第一个线程指令是一个设置的总线跟踪使能位（BTEB）指令的情况下，处理器设置与线程相对应的总线跟踪使能位。在设置BTEB的情况下，处理器确定第一个线程指令是否是符合条件的指令，并且在第一个线程指令是符合跟踪条件的指令的情况下，并且BTEB被设置，处理器设置一个窥探标记跟踪使能位（STTEB）。硬件跟踪监视器（HTM）监视总线事务，每个总线事务包括STTE。在监控总线事务包括一组STTEB的情况下，HTM将总线事务存储为跟踪数据。在监控总线事务包括复位STTEB的情况下，HTM不将总线事务存储为跟踪数据。

2. 发明申请

US20100268995A1 HARDWARE PROCESS TRACE FACILITY 有权
标题翻译：硬件工艺跟踪设备
公开(公告)号：US20100268995A1
公开(公告)日：2010-10-21
申请号：US12425075
申请日：2009-04-16
申请人： Benjiman L. Goodman , Sertac Cakici , Samuel I. Ward , Linton B. Ward, JR.
发明人： Benjiman L. Goodman , Sertac Cakici , Samuel I. Ward , Linton B. Ward, JR.
IPC分类号： G06F11/07
CPC分类号： G06F11/349 , G06F2201/87
摘要： A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread comprising an ordered series of thread instructions. In the event the first thread instruction is a set bus trace enable bit (BTEB) instruction, the processor sets a bus trace enable bit corresponding to the thread. In the event the BTEB is set, the processor determines whether the first thread instruction is a trace-eligible instruction and, in the event the first thread instruction is a trace-eligible instruction, and the BTEB is set, the processor sets a snoop tag trace enable bit (STTEB). A hardware trace monitor (HTM) monitors bus transactions, each bus transaction comprising a STTE. In the event a monitored bus transaction comprises a set STTEB, the HTM stores the bus transaction as trace data. In the event a monitored bus transaction comprises a reset STTEB, the HTM does not store the bus transaction as trace data.
摘要翻译：用于在多处理器系统中跟踪线程总线事务的方法包括由处理器解码线程的第一线程指令，所述线程包括有序序列的线程指令。在第一个线程指令是一个设置的总线跟踪使能位（BTEB）指令的情况下，处理器设置与线程相对应的总线跟踪使能位。在设置BTEB的情况下，处理器确定第一个线程指令是否是符合条件的指令，并且在第一个线程指令是符合跟踪条件的指令的情况下，并且BTEB被设置，处理器设置一个窥探标记跟踪使能位（STTEB）。硬件跟踪监视器（HTM）监视总线事务，每个总线事务包括STTE。在监控总线事务包括一组STTEB的情况下，HTM将总线事务存储为跟踪数据。在监控总线事务包括复位STTEB的情况下，HTM不将总线事务存储为跟踪数据。

3. 发明授权

US07925948B2 System and method for power reduction through power aware latch weighting 有权
标题翻译：通过功率感知锁存器加权降低功耗的系统和方法
公开(公告)号：US07925948B2
公开(公告)日：2011-04-12
申请号：US12206789
申请日：2008-09-09
申请人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
发明人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
IPC分类号： G01R31/28
CPC分类号： G06F11/263 , G01R31/3183
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.
摘要翻译：一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。不需要的分析模块识别DUT内的绝对不需要的锁存器，为所识别的不可用锁存器的位置分配一个加权值，并在一般测试中识别绝对不需要的位模式。电路分析模块根据相关位位置的加权值替代通用测试模式中识别的绝对不关心位，生成加权测试模式。测试向量模块基于加权测试模式生成测试向量，并且输入模块将测试向量应用于DUT。

4. 发明申请

US20100064190A1 System and Method for Power Reduction Through Power Aware Latch Weighting of Complex Sub-Circuits 有权
标题翻译：通过电力方面的功率降低系统和方法，复杂子电路的锁存加权
公开(公告)号：US20100064190A1
公开(公告)日：2010-03-11
申请号：US12206781
申请日：2008-09-09
申请人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, JR.
发明人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, JR.
IPC分类号： G01R31/3185 , G06F11/267
CPC分类号： G01R31/318536
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.
摘要翻译：一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。电路分析模块分析DUT内的子电路的DUT，并识别所识别的子电路的逻辑描述。不需要的分析模块耦合到电路分析模块，识别与所识别的子电路相关的绝对不需要的锁存器。子电路异常模块耦合到电路分析模块，并且基于所识别的绝对不需要的锁存器和所识别的子电路的逻辑描述来选择所识别的子电路的加权输入值。子电路异常模块存储用于子电路的选择的加权输入值，并将所选择的加权输入值与逻辑描述相关联。

5. 发明申请

US20100064189A1 System and Method for Power Reduction Through Power Aware Latch Weighting 有权
标题翻译：通过电源意识锁定加权降低功耗的系统和方法
公开(公告)号：US20100064189A1
公开(公告)日：2010-03-11
申请号：US12206789
申请日：2008-09-09
申请人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, JR.
发明人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, JR.
IPC分类号： G06F11/00
CPC分类号： G06F11/263 , G01R31/3183
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.
摘要翻译：一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。不需要的分析模块识别DUT内的绝对不需要的锁存器，为所识别的不可用锁存器的位置分配一个加权值，并在一般测试中识别绝对不需要的位模式。电路分析模块根据相关位位置的加权值替代通用测试模式中识别的绝对不关心位，生成加权测试模式。测试向量模块基于加权测试模式生成测试向量，并且输入模块将测试向量应用于DUT。

6. 发明授权

US07930610B2 System and method for power reduction through power aware latch weighting of complex sub-circuits 有权
标题翻译：通过复杂子电路的功率感知锁存器加权降低功耗的系统和方法
公开(公告)号：US07930610B2
公开(公告)日：2011-04-19
申请号：US12206781
申请日：2008-09-09
申请人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
发明人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.
摘要翻译：一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。电路分析模块分析DUT内的子电路的DUT，并识别所识别的子电路的逻辑描述。不需要的分析模块耦合到电路分析模块，识别与所识别的子电路相关的绝对不需要的锁存器。子电路异常模块耦合到电路分析模块，并且基于所识别的绝对不需要的锁存器和所识别的子电路的逻辑描述来选择所识别的子电路的加权输入值。子电路异常模块存储用于子电路的选择的加权输入值，并将所选择的加权输入值与逻辑描述相关联。

7. 发明授权

US08234612B2 Cone-aware spare cell placement using hypergraph connectivity analysis 有权
标题翻译：使用超图连接性分析的锥形识别备用单元布局
公开(公告)号：US08234612B2
公开(公告)日：2012-07-31
申请号：US12862949
申请日：2010-08-25
申请人： Benjiman L. Goodman , Nathaniel D. Hieter , Jeremy T. Hopkins , Samuel I. Ward
发明人： Benjiman L. Goodman , Nathaniel D. Hieter , Jeremy T. Hopkins , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/02 , G06F2217/72
摘要： Spare cells are placed in an IC design by assigning different spare utilization rates to logic cones, applying the rates to corresponding spare cell regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a spare cell at the overlapping region having the highest spare utilization rate. The best location for the spare cell is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The spare cell is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to spare cell location, and inserting the next spare cell at a region corresponding to the node which then has the greatest number of connected edges.
摘要翻译：通过向逻辑锥分配不同的备用利用率来将备用单元放置在IC设计中，将速率应用于圆锥体中的小区周围的相应备用单元区域，识别来自不同逻辑锥的区域的任何重叠，以及在重叠处插入备用单元具有最高备用利用率的区域。使用超图来计算备用单元的最佳位置，其中单元是边缘，并且区域是节点。由另一个节点主导的任何节点被去除，其边缘被扩展到主导节点。备用单元插入具有最多边缘的区域（边缘可以加权）。该过程重复地重复，通过去除连接到备用单元位置的节点来更新超图，并且将下一个备用单元插入到与具有最大连接边数的节点相对应的区域。

8. 发明申请

US20120054707A1 CONE-AWARE SPARE CELL PLACEMENT USING HYPERGRAPH CONNECTIVITY ANALYSIS 有权
标题翻译：使用HYPERGRAPH连接分析的CONE-AWARE SPARE CELL PLACEMENT
公开(公告)号：US20120054707A1
公开(公告)日：2012-03-01
申请号：US12862949
申请日：2010-08-25
申请人： Benjiman L. Goodman , Nathaniel D. Hieter , Jeremy T. Hopkins , Samuel I. Ward
发明人： Benjiman L. Goodman , Nathaniel D. Hieter , Jeremy T. Hopkins , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/02 , G06F2217/72
摘要： Spare cells are placed in an IC design by assigning different spare utilization rates to logic cones, applying the rates to corresponding spare cell regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a spare cell at the overlapping region having the highest spare utilization rate. The best location for the spare cell is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The spare cell is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to spare cell location, and inserting the next spare cell at a region corresponding to the node which then has the greatest number of connected edges.
摘要翻译：通过向逻辑锥分配不同的备用利用率来将备用单元放置在IC设计中，将速率应用于圆锥体中的小区周围的相应备用单元区域，识别来自不同逻辑锥的区域的任何重叠，以及在重叠处插入备用单元具有最高备用利用率的区域。使用超图来计算备用单元的最佳位置，其中单元是边缘，并且区域是节点。由另一个节点主导的任何节点被去除，其边缘被扩展到主导节点。备用单元插入具有最多边缘的区域（边缘可以加权）。该过程重复地重复，通过去除连接到备用单元位置的节点来更新超图，并且将下一个备用单元插入到与具有最大连接边数的节点相对应的区域。

9. 发明授权

US08775904B2 Efficient storage of meta-bits within a system memory 有权
标题翻译：元位在系统存储器内的高效存储
公开(公告)号：US08775904B2
公开(公告)日：2014-07-08
申请号：US13313364
申请日：2011-12-07
申请人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
发明人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
IPC分类号： G11C29/42 , G06F11/10 , G11C29/54 , G11C29/04
CPC分类号： G06F11/1076 , G06F11/1064 , G06F12/0815 , G06F12/0895 , G11C2029/0411
摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.
摘要翻译：提供了用于在系统存储器内有效存储元位的机制。这些机制将L / G位和SUE位组合以形成元位。机制然后在第一个数据周期上确定高速缓存行的本地/全局状态。这些机制将数据转发到请求的高速缓存，并且请求高速缓存可以基于高速缓存行的本地/全局状态全局重新发出请求。这些机制然后在数据的第二个或随后的周期中确定高速缓存行的特殊的不可校正错误状态。机制执行错误处理，而不管请求是否在全球重新发布。

10. 发明授权

US08683128B2 Memory bus write prioritization 有权
公开(公告)号：US08683128B2
公开(公告)日：2014-03-25
申请号：US12775511
申请日：2010-05-07
申请人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0888 , Y02D10/13
摘要： A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.

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