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1. 发明授权

US08296578B1 Method and apparatus for communicating data between stacked integrated circuits 有权
标题翻译：用于在堆叠集成电路之间传送数据的方法和装置
公开(公告)号：US08296578B1
公开(公告)日：2012-10-23
申请号：US12534587
申请日：2009-08-03
申请人： Bernard J. New
发明人： Bernard J. New
IPC分类号： G06F12/14
CPC分类号： G06F21/79 , G06F17/5054 , G06F17/5068 , H01L2224/0557 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568
摘要： Method and apparatus for communicating data between vertically stacked integrated circuits is described. In some examples, a method of configuring an integrated circuit which is a first die includes obtaining configuration data at configuration resources of the integrated circuit from a non-volatile memory on a second die through an integration tile of the integrated circuit, the second die being vertically stacked on the first die; storing the configuration data in at least one register as the configuration data is obtained by the configuration resources; and loading the configuration data from the at least one register to a configuration memory of the integrated circuit to configure programmable resources of the integrated circuit.
摘要翻译：描述了用于在垂直堆叠集成电路之间传送数据的方法和装置。在一些示例中，配置作为第一管芯的集成电路的方法包括通过集成电路的集成块从第二管芯上的非易失性存储器获得集成电路的配置资源的配置数据，第二管芯为垂直堆叠在第一个模具上; 通过配置资源获取配置数据，将配置数据存储在至少一个寄存器中; 以及将所述配置数据从所述至少一个寄存器加载到所述集成电路的配置存储器，以配置所述集成电路的可编程资源。

2. 发明授权

US08089299B1 Integrated circuit with through-die via interface for die stacking and cross-track routing 有权
标题翻译：集成电路，具有通孔接口，用于芯片堆叠和交叉轨道路由
公开(公告)号：US08089299B1
公开(公告)日：2012-01-03
申请号：US12436918
申请日：2009-05-07
申请人： Arifur Rahman , Bernard J. New
发明人： Arifur Rahman , Bernard J. New
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17796
摘要： An integrated circuit die is described that includes an array of tiles arranged in columns. The integrated circuit die includes interface tiles having at least one row of through die vias. The integrated circuit die includes metal layers that include horizontal wiring tracks and metal layers that include vertical wiring tracks. At least some of the metal layers having vertical wiring segments include horizontal wiring segments. Each horizontal wiring segment is coupled to a first wiring segment of a horizontal wiring track that is interrupted by the at least one row of through die vias and is coupled to a second wiring segment of the horizontal wiring track that is interrupted by the at least one row of through die vias. Each horizontal wiring segment extends between the at least one row of through die vias and at least one row of through die vias in an adjoining interface tile.
摘要翻译：描述了一种集成电路管芯，其包括以列排列的瓦片阵列。集成电路管芯包括具有至少一排通孔的界面砖。集成电路管芯包括包括水平布线轨道和包括垂直布线轨道的金属层的金属层。具有垂直布线段的至少一些金属层包括水平布线段。每个水平布线段耦合到水平布线轨道的第一布线段，该第一布线段由至少一行贯通管道通孔中断，并且连接到由至少一个中断的水平布线轨道的第二布线段一排穿过通孔。每个水平布线段在至少一排通孔通孔之间延伸，并且在邻接的界面砖中延伸至少一排通孔。

3. 发明授权

US07984407B1 Programmable device with contact via programming 有权
标题翻译：可编程器件通过编程接触
公开(公告)号：US07984407B1
公开(公告)日：2011-07-19
申请号：US11880953
申请日：2007-07-24
申请人： Bernard J. New
发明人： Bernard J. New
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5063 , G06F2217/78
摘要： A programmable device with contact via programming to reduce leakage current and a method for reducing standby power for such programmable device are described. Configuration memory cells are identified responsive to instantiation of a user design in a test platform of the programmable device. The programmable device is via programmed during manufacturing thereof to not couple for programmability a first portion of the configuration memory cells and to form a first portion of the user design associated with the first portion of the configuration memory cells as hard-wired and to couple for programmability a second portion of the configuration memory cells for subsequent instantiation of a second portion of the user design in the programmable device.
摘要翻译：描述了具有通过编程进行接触以减少泄漏电流的可编程装置以及用于降低这种可编程装置的待机功率的方法。响应于可编程设备的测试平台中的用户设计的实例化来识别配置存储器单元。可编程设备通过在其制造期间被编程而不能配置存储器单元的第一部分的可编程性，并且形成与配置存储器单元的第一部分相关联的用户设计的第一部分作为硬接线并且耦合可编程性地配置存储器单元的第二部分，用于可编程设备中用户设计的第二部分的后续实例化。

4. 发明授权

US07930661B1 Software model for a hybrid stacked field programmable gate array 有权
标题翻译：混合堆叠现场可编程门阵列的软件模型
公开(公告)号：US07930661B1
公开(公告)日：2011-04-19
申请号：US12185511
申请日：2008-08-04
申请人： Stephen M. Trimberger , Arifur Rahman , Bernard J. New
发明人： Stephen M. Trimberger , Arifur Rahman , Bernard J. New
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A software model (620) of a stacked integrated circuit system (600) includes a first integrated circuit die (602) connected to a second integrated circuit die (604) through an interchip communication interface (606). A software model of the first integrated circuit die includes an integrated circuit resource (614) and an internal interface (150). A software model of the second integrated circuit die includes a stacked resource (618). The software model of the internal interface is configurable to connect the stacked resource of the second integrated circuit die to the integrated circuit resource through the interchip communication interface.
摘要翻译：层叠集成电路系统（600）的软件模型（620）包括通过芯片间通信接口（606）连接到第二集成电路管芯（604）的第一集成电路管芯（602）。第一集成电路管芯的软件模型包括集成电路资源（614）和内部接口（150）。第二集成电路管芯的软件模型包括堆叠资源（618）。内部接口的软件模型可配置为通过芯片间通信接口将第二个集成电路管芯的堆叠资源连接到集成电路资源。

5. 发明授权

US07853634B2 Digital signal processing circuit having a SIMD circuit 有权
标题翻译：具有SIMD电路的数字信号处理电路
公开(公告)号：US07853634B2
公开(公告)日：2010-12-14
申请号：US11433331
申请日：2006-05-12
申请人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
发明人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.
摘要翻译：公开了具有单指令多数据（SIMD）的集成电路（IC）。 SIMD电路包括：由第一操作码控制的多个复用器; 以及耦合到所述多个多路复用器并由第二操作码控制的算术逻辑单元（ALU）; 并且其中所述ALU具有多个加法器，其中所述多个加法器由所述第二操作码的某些位控制，并且其中所述多个加法器中的第一加法器添加多个输入位以产生第一求和位和第一进位位所述第一加法器与所述多个加法器的其它加法器同时运行。

6. 发明授权

US07840627B2 Digital signal processing circuit having input register blocks 有权
标题翻译：具有输入寄存器块的数字信号处理电路
公开(公告)号：US07840627B2
公开(公告)日：2010-11-23
申请号：US11432823
申请日：2006-05-12
申请人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
发明人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.
摘要翻译：一种集成电路，包括具有耦合到第一算术逻辑单元（ALU）电路的第一和第二寄存器块的数字信号处理元件（DSPE）; 与顶部DSPE相邻的中间DSPE具有耦合到第二ALU电路的第三和第四寄存器块，其中第三寄存器块耦合到第一寄存器块，并且第四寄存器块寄存器块耦合到第二寄存器块 ; 以及与中间DSPE相邻的底部DSPE，具有耦合到第三ALU电路的第五和第六寄存器块，其中第五寄存器块耦合到第三寄存器块，并且第六寄存器块寄存器块耦合到第四寄存器块。

7. 发明授权

US07567997B2 Applications of cascading DSP slices 有权
标题翻译：级联DSP片的应用
公开(公告)号：US07567997B2
公开(公告)日：2009-07-28
申请号：US11019518
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/48
CPC分类号： G06F7/5443
摘要： In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.
摘要翻译：在一个实施例中，公开了一种IC，其包括多个级联的数字信号处理片，其中每个片具有经由多路复用器耦合到加法器的乘法器，并且每个片与直接连接到相邻片; 以及用于通过例如opmode来配置多个数字信号处理片以执行一个或多个数学运算的装置。该IC允许实现一些基本的数学函数，例如加，减，乘和除。可以使用一个或多个DSP片段来实现许多其它应用，例如，累加，乘法累加（MACC），宽多路复用器，桶形移位器，计数器和折叠，抽取和内插FIR等等。

8. 发明授权

US07248073B2 Configurable logic element with expander structures 有权
标题翻译：具有扩展器结构的可配置逻辑元件
公开(公告)号：US07248073B2
公开(公告)日：2007-07-24
申请号：US11585534
申请日：2006-10-24
申请人： Bernard J. New , Ralph D. Wittig , Sundararajarao Mohan
发明人： Bernard J. New , Ralph D. Wittig , Sundararajarao Mohan
IPC分类号： H01L25/00 , H03K19/77
CPC分类号： H03K19/17748 , H03K19/1731 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.
摘要翻译：用于现场可编程门阵列（FPGA）的可配置逻辑元件（CLE）包括“扩展器”，即允许逻辑块之间的快速信号通信的连接器。扩展器允许多个逻辑块或其部分的可配置互连形成可以实现诸如PAL，查找表，多路复用器，三态缓冲器和存储器之类的大型用户电路的单个逻辑实体。一个实施例包括可配置逻辑块。在第一模式中，逻辑块提供具有N个共享输入和两个单独输出的两个N输入LUT。然后使用扩展器组合输出以产生（N + 1） - 输入功能。在第二模式中，逻辑块提供具有M个非共享输入的两个N输入LUT。可选的第三模式基于N个输入信号的值提供多个产品项输出信号。

9. 发明授权

US07062586B2 Method and apparatus for communication within a programmable logic device using serial transceivers 有权
标题翻译：使用串行收发器的可编程逻辑器件内的通信方法和装置
公开(公告)号：US07062586B2
公开(公告)日：2006-06-13
申请号：US10420418
申请日：2003-04-21
申请人： Adam P. Donlin , Bernard J. New
发明人： Adam P. Donlin , Bernard J. New
IPC分类号： G06F13/38 , H03K19/177
CPC分类号： H03K19/17736
摘要： Method and apparatus for communication within a programmable logic device using serial transceivers is described. In an example, an integrated circuit includes a first module and a second module. The first module and the second module each include a transceiver coupled to a serial/parallel interface, with each transceiver configured with at least one signal conductor for serial communication between the first module and the second module. The first module and the second module are configured to communicate with one another asynchronously. Each transceiver is configured to communicate with its respective serial/parallel interface in a synchronous time domain.
摘要翻译：描述了使用串行收发器的可编程逻辑器件内的通信方法和装置。在一个示例中，集成电路包括第一模块和第二模块。第一模块和第二模块各自包括耦合到串行/并行接口的收发器，每个收发器配置有用于第一模块和第二模块之间的串行通信的至少一个信号导体。第一模块和第二模块被配置为异步地彼此通信。每个收发器被配置为在同步时域中与其各自的串行/并行接口进行通信。

10. 发明授权

US06362648B1 Multiplexer for implementing logic functions in a programmable logic device 有权
标题翻译：用于在可编程逻辑器件中实现逻辑功能的多路复用器
公开(公告)号：US06362648B1
公开(公告)日：2002-03-26
申请号：US09712038
申请日：2000-11-13
申请人： Bernard J. New , Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
发明人： Bernard J. New , Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
IPC分类号： G06F738
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/1778
摘要： The invention allows the implementation of common wide logic functions using only two function generators of a field programmable gate array. One embodiment of the invention provides a structure for implementing a wide AND-gate in an FPGA configurable logic element (CLE) or portion thereof that includes no more than two function generators. First and second function generators are configured as AND-gates, the output signals (first and second AND signals) being combined in a 2-to-1 multiplexer controlled by the first AND signal, “0” selecting the first AND signal and “1” selecting the second AND signal. Therefore, a wide AND-gate is provided having a number of input signals equal to the total number of input signals for the two function generators. In another embodiment, a wide OR-gate is provided by configuring the function generators as OR-gates and controlling the multiplexer using the second OR signal.
摘要翻译：本发明允许仅使用现场可编程门阵列的两个函数发生器实现普通的宽逻辑功能。本发明的一个实施例提供了一种用于在FPGA可配置逻辑元件（CLE）或其部分中实现宽的与门的结构，其包括不超过两个功能发生器。第一和第二功能发生器被配置为与门，输出信号（第一和第二AND信号）被组合在由第一AND信号控制的2对1多路复用器中，选择第一AND信号为“0”和“1” “选择第二个AND信号。因此，提供了具有等于两个功能发生器的输入信号的总数的多个输入信号的宽AND门。在另一个实施例中，通过将功能发生器配置为OR门并使用第二OR信号来控制多路复用器来提供宽的或门。

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