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1. 发明授权

US07733724B2 Controlling global bit line pre-charge time for high speed eDRAM 有权
标题翻译：控制高速eDRAM的全局位线预充电时间
公开(公告)号：US07733724B2
公开(公告)日：2010-06-08
申请号：US11970188
申请日：2008-01-07
申请人： Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
发明人： Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/1048
摘要： A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the memory cell, wherein the steps of starting the first GBL pre-charge and enabling the word line have a first time interval. The read operation includes starting a second GBL pre-charge on the GBL; and after the second GBL pre-charge is started, enabling the word line to read from the memory cell, wherein the steps of starting the second GBL pre-charge and enabling the word line have a second time interval. The first time interval is greater than the second time interval.
摘要翻译：操作存储器的方法包括对存储器单元执行写入操作和读取操作。写入操作包括在GBL上启动第一个全局位线（GBL）预充电; 并且在开始第一GBL预充电之后，使得字线能够写入存储单元，其中启动第一GBL预充电和启用字线的步骤具有第一时间间隔。读取操作包括在GBL上启动第二个GBL预充电; 并且在开始第二GBL预充电之后，使得字线能够从存储器单元读取，其中启动第二GBL预充电和使字线的步骤具有第二时间间隔。第一时间间隔大于第二时间间隔。

2. 发明授权

US07848166B2 Circuit and method for a Vdd level memory sense amplifier 有权
标题翻译：用于Vdd级存储器读出放大器的电路和方法
公开(公告)号：US07848166B2
公开(公告)日：2010-12-07
申请号：US12046276
申请日：2008-03-11
申请人： Kuoyuan Peter Hsu , Young Suk Kim , Bing Wang , Ming Chieh Huang
发明人： Kuoyuan Peter Hsu , Young Suk Kim , Bing Wang , Ming Chieh Huang
IPC分类号： G11C7/08 , G11C7/12
CPC分类号： G11C11/4091 , G11C7/08 , G11C7/12 , G11C11/4094 , G11C11/4097
摘要： A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense amplifier is coupled to the bit line and the complementary bit line. A control signal couples a reference voltage to the complementary bit line. A positive precharge voltage is applied to the bit line and complementary bit line prior to the sense amplifier being enabled. The memory cell outputs a voltage to the bit line responsive to a word line, and the sense amplifier senses the differential voltage between the bit line and the complementary bit line responsive to a sense enable signal. A voltage regulator for generating the reference voltage, preferably about 80% of a positive supply voltage, is disclosed. A method of sensing data stored by a memory cell is disclosed.
摘要翻译：公开了一种用于感测由存储器单元存储的电荷的读出放大器的电路和方法。存储单元耦合到位线，互补位线和差分读出放大器耦合到位线和互补位线。控制信号将参考电压耦合到互补位线。在读出放大器使能之前，将正预充电电压施加到位线和互补位线。存储单元响应于字线向位线输出电压，并且感测放大器响应于感测使能信号来感测位线和互补位线之间的差分电压。公开了用于产生参考电压的电压调节器，优选地为正电源电压的约80％。公开了一种感测由存储器单元存储的数据的方法。

3. 发明授权

US08780652B2 Signal tracking in write operations of memory cells 有权
标题翻译：存储单元的写入操作中的信号跟踪
公开(公告)号：US08780652B2
公开(公告)日：2014-07-15
申请号：US13418968
申请日：2012-03-13
申请人： Bing Wang , Kuoyuan (Peter) Hsu , Young Suk Kim
发明人： Bing Wang , Kuoyuan (Peter) Hsu , Young Suk Kim
IPC分类号： G11C7/00 , G11C7/22
CPC分类号： G11C7/22 , G11C7/12 , G11C7/222 , G11C8/08 , G11C11/419 , G11C2207/005 , G11C2207/2254
摘要： In a method, a first edge of a first tracking signal in a first direction of a memory array is generated. A first edge of a second tracking signal in a second direction of the memory array is generated. A first edge of a write-timing control signal is generated based on a slower edge of the first edge the first tracking signal and of the first edge of the second tracking signal. The first edge of the write-timing control signal is used to generate a second edge of the second tracking signal.
摘要翻译：在一种方法中，产生在存储器阵列的第一方向上的第一跟踪信号的第一边缘。生成存储器阵列的第二方向上的第二跟踪信号的第一边缘。基于第一边缘的较慢边缘和第二跟踪信号的第一边缘产生写时序控制信号的第一边沿。写定时控制信号的第一边用于产生第二跟踪信号的第二边。

4. 发明申请

US20090231939A1 Circuit and Method for a Vdd Level Memory Sense Amplifier 有权
标题翻译：用于Vdd级存储器检测放大器的电路和方法
公开(公告)号：US20090231939A1
公开(公告)日：2009-09-17
申请号：US12046276
申请日：2008-03-11
申请人： Kuoyuan Peter Hsu , Young Suk Kim , Bing Wang , Ming Chieh Huang
发明人： Kuoyuan Peter Hsu , Young Suk Kim , Bing Wang , Ming Chieh Huang
IPC分类号： G11C7/08 , G11C7/12
CPC分类号： G11C11/4091 , G11C7/08 , G11C7/12 , G11C11/4094 , G11C11/4097
摘要： A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense amplifier is coupled to the bit line and the complementary bit line. A control signal couples a reference voltage to the complementary bit line. A positive precharge voltage is applied to the bit line and complementary bit line prior to the sense amplifier being enabled. The memory cell outputs a voltage to the bit line responsive to a word line, and the sense amplifier senses the differential voltage between the bit line and the complementary bit line responsive to a sense enable signal. A voltage regulator for generating the reference voltage, preferably about 80% of a positive supply voltage, is disclosed. A method of sensing data stored by a memory cell is disclosed.
摘要翻译：公开了一种用于感测由存储器单元存储的电荷的读出放大器的电路和方法。存储单元耦合到位线，互补位线和差分读出放大器耦合到位线和互补位线。控制信号将参考电压耦合到互补位线。在读出放大器使能之前，将正预充电电压施加到位线和互补位线。存储单元响应于字线向位线输出电压，并且感测放大器响应于感测使能信号来感测位线和互补位线之间的差分电压。公开了用于产生参考电压的电压调节器，优选地为正电源电压的约80％。公开了一种感测由存储器单元存储的数据的方法。

5. 发明申请

US20090141570A1 Controlling Global Bit Line Pre-Charge Time for High Speed eDRAM 有权
标题翻译：控制高速eDRAM的全局位线预充电时间
公开(公告)号：US20090141570A1
公开(公告)日：2009-06-04
申请号：US11970188
申请日：2008-01-07
申请人： Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
发明人： Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/1048
摘要： A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the memory cell, wherein the steps of starting the first GBL pre-charge and enabling the word line have a first time interval. The read operation includes starting a second GBL pre-charge on the GBL; and after the second GBL pre-charge is started, enabling the word line to read from the memory cell, wherein the steps of starting the second GBL pre-charge and enabling the word line have a second time interval. The first time interval is greater than the second time interval.
摘要翻译：操作存储器的方法包括对存储器单元执行写入操作和读取操作。写入操作包括在GBL上启动第一个全局位线（GBL）预充电; 并且在开始第一GBL预充电之后，使得字线能够写入存储单元，其中启动第一GBL预充电和启用字线的步骤具有第一时间间隔。读取操作包括在GBL上启动第二个GBL预充电; 并且在开始第二GBL预充电之后，使得字线能够从存储器单元读取，其中启动第二GBL预充电和使字线的步骤具有第二时间间隔。第一时间间隔大于第二时间间隔。

6. 发明授权

US08279686B2 Memory circuits, systems, and methods for providing bit line equalization voltages 有权
标题翻译：用于提供位线均衡电压的存储器电路，系统和方法
公开(公告)号：US08279686B2
公开(公告)日：2012-10-02
申请号：US12692512
申请日：2010-01-22
申请人： Kuoyuan Peter Hsu , TaeHyung Jung , Douk Hyoun Ryu , Young Suk Kim
发明人： Kuoyuan Peter Hsu , TaeHyung Jung , Douk Hyoun Ryu , Young Suk Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C11/4076
摘要： A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell.
摘要翻译：存储电路包括至少一个用于存储表示数据的电荷的存储单元。存储单元与字线和第一位线耦合。至少一个位线均衡晶体管耦合在第一位线和第二位线之间。位线均衡电路与位线均衡晶体管耦合。位线均衡电路被配置为向位线均衡晶体管提供脉冲，以在存储单元的访问周期之前的待机期间基本上均衡第一位线和第二位线的电压。

7. 发明授权

US08305827B2 Dual rail memory 有权
标题翻译：双轨内存
公开(公告)号：US08305827B2
公开(公告)日：2012-11-06
申请号：US12835197
申请日：2010-07-13
申请人： Derek C. Tao , Kuoyuan (Peter) Hsu , Dong Sik Jeong , Young Suk Kim , Young Seog Kim , Yukit Tang
发明人： Derek C. Tao , Kuoyuan (Peter) Hsu , Dong Sik Jeong , Young Suk Kim , Young Seog Kim , Yukit Tang
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, and a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes are electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.
摘要翻译：存储器阵列包括以多行和多列布置的多个存储单元。多列的列包括被配置为提供第一电压的第一电源节点，被配置为提供第二电压的第二电源节点和电耦合在一起并被配置为接收第一电压的多个内部供电节点，该列中的多个存储单元的第二电压和多个内部接地节点。内部接地节点电耦合在一起并且被配置为为列中的多个存储器单元提供至少两个电流路径。

8. 发明授权

US08587991B2 Recycling charges 有权
标题翻译：回收费用
公开(公告)号：US08587991B2
公开(公告)日：2013-11-19
申请号：US13429082
申请日：2012-03-23
申请人： Young Seog Kim , Kuoyuan (Peter) Hsu , Derek C. Tao , Young Suk Kim
发明人： Young Seog Kim , Kuoyuan (Peter) Hsu , Derek C. Tao , Young Suk Kim
IPC分类号： G11C11/00 , G11C7/00 , G11C5/14
CPC分类号： G11C11/412
摘要： A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.
摘要翻译：电路包括第一节点; 第二个节点; 具有耦合到第一节点的源极的第一PMOS晶体管，耦合到第一控制晶体管的漏极和由第一电压驱动的栅极; 以及第一NMOS晶体管，其具有耦合到第二节点的源极，耦合到第一控制晶体管的漏极和由第二电压驱动的栅极。第一PMOS晶体管被配置为基于第一节点处的第一电压和第一节点电压自动关闭。第一NMOS晶体管被配置为基于第二节点处的第二电压和第二节点电压自动关闭。当第一PMOS晶体管，控制晶体管和第一NMOS晶体管导通时，第一节点电压降低，而第二电压升高。

9. 发明授权

US08976614B2 Tracking scheme for memory 有权
标题翻译：内存跟踪方案
公开(公告)号：US08976614B2
公开(公告)日：2015-03-10
申请号：US13026021
申请日：2011-02-11
申请人： Yong Zhang , Derek C. Tao , Dongsik Jeong , Young Suk Kim , Kuoyuan (Peter) Hsu
发明人： Yong Zhang , Derek C. Tao , Dongsik Jeong , Young Suk Kim , Kuoyuan (Peter) Hsu
IPC分类号： G11C7/06 , G11C7/22 , G11C11/419
CPC分类号： G11C7/227 , G11C11/419
摘要： A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row.
摘要翻译：存储器具有用于读取跟踪操作的跟踪电路。存储器包括存储位单元阵列，跟踪列，跟踪行，耦合到存储器位单元阵列和跟踪行的读出放大器行以及读出放大器使能逻辑。存储器还包括耦合到跟踪列和读出放大器使能逻辑的跟踪位线，以及耦合到跟踪行和读出放大器使能逻辑的跟踪字线。跟踪电路被配置为沿着跟踪行在行时间延迟之前跟踪沿着跟踪列的列时间延迟。

10. 发明申请

US20100202220A1 MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR PROVIDING BIT LINE EQUALIZATION VOLTAGES 有权
标题翻译：用于提供线路均衡电压的存储器电路，系统和方法
公开(公告)号：US20100202220A1
公开(公告)日：2010-08-12
申请号：US12692512
申请日：2010-01-22
申请人： Kuoyuan Peter HSU , TaeHyung Jung , Douk Hyoun Ryu , Young Suk Kim
发明人： Kuoyuan Peter HSU , TaeHyung Jung , Douk Hyoun Ryu , Young Suk Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C11/4076
摘要： A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell.
摘要翻译：存储电路包括至少一个用于存储表示数据的电荷的存储单元。存储单元与字线和第一位线耦合。至少一个位线均衡晶体管耦合在第一位线和第二位线之间。位线均衡电路与位线均衡晶体管耦合。位线均衡电路被配置为向位线均衡晶体管提供脉冲，以在存储单元的访问周期之前的待机期间基本上均衡第一位线和第二位线的电压。

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