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1. 发明授权

US07848166B2 Circuit and method for a Vdd level memory sense amplifier 有权
标题翻译：用于Vdd级存储器读出放大器的电路和方法
公开(公告)号：US07848166B2
公开(公告)日：2010-12-07
申请号：US12046276
申请日：2008-03-11
申请人： Kuoyuan Peter Hsu , Young Suk Kim , Bing Wang , Ming Chieh Huang
发明人： Kuoyuan Peter Hsu , Young Suk Kim , Bing Wang , Ming Chieh Huang
IPC分类号： G11C7/08 , G11C7/12
CPC分类号： G11C11/4091 , G11C7/08 , G11C7/12 , G11C11/4094 , G11C11/4097
摘要： A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense amplifier is coupled to the bit line and the complementary bit line. A control signal couples a reference voltage to the complementary bit line. A positive precharge voltage is applied to the bit line and complementary bit line prior to the sense amplifier being enabled. The memory cell outputs a voltage to the bit line responsive to a word line, and the sense amplifier senses the differential voltage between the bit line and the complementary bit line responsive to a sense enable signal. A voltage regulator for generating the reference voltage, preferably about 80% of a positive supply voltage, is disclosed. A method of sensing data stored by a memory cell is disclosed.
摘要翻译：公开了一种用于感测由存储器单元存储的电荷的读出放大器的电路和方法。存储单元耦合到位线，互补位线和差分读出放大器耦合到位线和互补位线。控制信号将参考电压耦合到互补位线。在读出放大器使能之前，将正预充电电压施加到位线和互补位线。存储单元响应于字线向位线输出电压，并且感测放大器响应于感测使能信号来感测位线和互补位线之间的差分电压。公开了用于产生参考电压的电压调节器，优选地为正电源电压的约80％。公开了一种感测由存储器单元存储的数据的方法。

2. 发明授权

US08780652B2 Signal tracking in write operations of memory cells 有权
标题翻译：存储单元的写入操作中的信号跟踪
公开(公告)号：US08780652B2
公开(公告)日：2014-07-15
申请号：US13418968
申请日：2012-03-13
申请人： Bing Wang , Kuoyuan (Peter) Hsu , Young Suk Kim
发明人： Bing Wang , Kuoyuan (Peter) Hsu , Young Suk Kim
IPC分类号： G11C7/00 , G11C7/22
CPC分类号： G11C7/22 , G11C7/12 , G11C7/222 , G11C8/08 , G11C11/419 , G11C2207/005 , G11C2207/2254
摘要： In a method, a first edge of a first tracking signal in a first direction of a memory array is generated. A first edge of a second tracking signal in a second direction of the memory array is generated. A first edge of a write-timing control signal is generated based on a slower edge of the first edge the first tracking signal and of the first edge of the second tracking signal. The first edge of the write-timing control signal is used to generate a second edge of the second tracking signal.
摘要翻译：在一种方法中，产生在存储器阵列的第一方向上的第一跟踪信号的第一边缘。生成存储器阵列的第二方向上的第二跟踪信号的第一边缘。基于第一边缘的较慢边缘和第二跟踪信号的第一边缘产生写时序控制信号的第一边沿。写定时控制信号的第一边用于产生第二跟踪信号的第二边。

3. 发明申请

US20090231939A1 Circuit and Method for a Vdd Level Memory Sense Amplifier 有权
标题翻译：用于Vdd级存储器检测放大器的电路和方法
公开(公告)号：US20090231939A1
公开(公告)日：2009-09-17
申请号：US12046276
申请日：2008-03-11
申请人： Kuoyuan Peter Hsu , Young Suk Kim , Bing Wang , Ming Chieh Huang
发明人： Kuoyuan Peter Hsu , Young Suk Kim , Bing Wang , Ming Chieh Huang
IPC分类号： G11C7/08 , G11C7/12
CPC分类号： G11C11/4091 , G11C7/08 , G11C7/12 , G11C11/4094 , G11C11/4097
摘要： A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense amplifier is coupled to the bit line and the complementary bit line. A control signal couples a reference voltage to the complementary bit line. A positive precharge voltage is applied to the bit line and complementary bit line prior to the sense amplifier being enabled. The memory cell outputs a voltage to the bit line responsive to a word line, and the sense amplifier senses the differential voltage between the bit line and the complementary bit line responsive to a sense enable signal. A voltage regulator for generating the reference voltage, preferably about 80% of a positive supply voltage, is disclosed. A method of sensing data stored by a memory cell is disclosed.
摘要翻译：公开了一种用于感测由存储器单元存储的电荷的读出放大器的电路和方法。存储单元耦合到位线，互补位线和差分读出放大器耦合到位线和互补位线。控制信号将参考电压耦合到互补位线。在读出放大器使能之前，将正预充电电压施加到位线和互补位线。存储单元响应于字线向位线输出电压，并且感测放大器响应于感测使能信号来感测位线和互补位线之间的差分电压。公开了用于产生参考电压的电压调节器，优选地为正电源电压的约80％。公开了一种感测由存储器单元存储的数据的方法。

4. 发明申请

US20090141570A1 Controlling Global Bit Line Pre-Charge Time for High Speed eDRAM 有权
标题翻译：控制高速eDRAM的全局位线预充电时间
公开(公告)号：US20090141570A1
公开(公告)日：2009-06-04
申请号：US11970188
申请日：2008-01-07
申请人： Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
发明人： Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/1048
摘要： A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the memory cell, wherein the steps of starting the first GBL pre-charge and enabling the word line have a first time interval. The read operation includes starting a second GBL pre-charge on the GBL; and after the second GBL pre-charge is started, enabling the word line to read from the memory cell, wherein the steps of starting the second GBL pre-charge and enabling the word line have a second time interval. The first time interval is greater than the second time interval.
摘要翻译：操作存储器的方法包括对存储器单元执行写入操作和读取操作。写入操作包括在GBL上启动第一个全局位线（GBL）预充电; 并且在开始第一GBL预充电之后，使得字线能够写入存储单元，其中启动第一GBL预充电和启用字线的步骤具有第一时间间隔。读取操作包括在GBL上启动第二个GBL预充电; 并且在开始第二GBL预充电之后，使得字线能够从存储器单元读取，其中启动第二GBL预充电和使字线的步骤具有第二时间间隔。第一时间间隔大于第二时间间隔。

5. 发明授权

US07733724B2 Controlling global bit line pre-charge time for high speed eDRAM 有权
标题翻译：控制高速eDRAM的全局位线预充电时间
公开(公告)号：US07733724B2
公开(公告)日：2010-06-08
申请号：US11970188
申请日：2008-01-07
申请人： Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
发明人： Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/1048
摘要： A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the memory cell, wherein the steps of starting the first GBL pre-charge and enabling the word line have a first time interval. The read operation includes starting a second GBL pre-charge on the GBL; and after the second GBL pre-charge is started, enabling the word line to read from the memory cell, wherein the steps of starting the second GBL pre-charge and enabling the word line have a second time interval. The first time interval is greater than the second time interval.
摘要翻译：操作存储器的方法包括对存储器单元执行写入操作和读取操作。写入操作包括在GBL上启动第一个全局位线（GBL）预充电; 并且在开始第一GBL预充电之后，使得字线能够写入存储单元，其中启动第一GBL预充电和启用字线的步骤具有第一时间间隔。读取操作包括在GBL上启动第二个GBL预充电; 并且在开始第二GBL预充电之后，使得字线能够从存储器单元读取，其中启动第二GBL预充电和使字线的步骤具有第二时间间隔。第一时间间隔大于第二时间间隔。

6. 发明申请

US20140032871A1 TRACKING MECHANISM FOR WRITING TO A MEMORY CELL 有权
标题翻译：跟踪机制写入记忆体
公开(公告)号：US20140032871A1
公开(公告)日：2014-01-30
申请号：US13560461
申请日：2012-07-27
申请人： Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
发明人： Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
IPC分类号： G06F12/00 , G11C7/00
CPC分类号： G11C7/222 , G11C7/12 , G11C7/227 , G11C11/419
摘要： A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell.
摘要翻译：电路包括跟踪写入电路和写入电路。基于跟踪写入电路的跟踪信号产生写入电路的各种写入信号。写信号用于存储单元的写入操作。

7. 发明申请

US20110199835A1 No-Disturb Bit Line Write for Improving Speed of eDRAM 有权
标题翻译：无干扰位线写入以提高eDRAM的速度
公开(公告)号：US20110199835A1
公开(公告)日：2011-08-18
申请号：US13094389
申请日：2011-04-26
申请人： Subramani Kengeri , Kuoyuan (Peter) Hsu , Bing Wang
发明人： Subramani Kengeri , Kuoyuan (Peter) Hsu , Bing Wang
IPC分类号： G11C7/06
CPC分类号： G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C2207/104
摘要： A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit line and a second global bit line coupled to the first and the second local bit lines, respectively. The method further includes starting an equalization to equalize voltages on the first and the second local bit lines; stopping the equalization; and after the step of starting the equalization and before the step of stopping the equalization, writing values from the first and the second global bit lines to the first and the second local bit lines.
摘要翻译：一种操作存储电路的方法包括提供存储电路。存储电路包括存储单元; 连接到存储单元的字线; 连接到存储单元的第一局部位线和第二局部位线; 以及分别耦合到第一和第二局部位线的第一全局位线和第二全局位线。该方法还包括开始均衡以均衡第一和第二局部位线上的电压; 停止均衡并且在开始均衡的步骤之后，在停止均衡的步骤之前，将值从第一和第二全局位线写入第一和第二局部位线。

8. 发明授权

US08619477B2 Two-port SRAM write tracking scheme 有权
标题翻译：双端口SRAM写入跟踪方案
公开(公告)号：US08619477B2
公开(公告)日：2013-12-31
申请号：US12839624
申请日：2010-07-20
申请人： Bing Wang , Kuoyuan (Peter) Hsu , Derek C. Tao
发明人： Bing Wang , Kuoyuan (Peter) Hsu , Derek C. Tao
IPC分类号： G11C7/10
CPC分类号： G11C11/419 , G11C11/413
摘要： A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is coupled to the memory cells for determining a write time of the memory cells. The write tracking control circuit is capable of receiving an input voltage and providing an output voltage. The respective RWL and the respective WWL of each memory cell are asserted during a write tracking operation.
摘要翻译：静态随机存取存储器（SRAM）包括共享读位线（RBL）和写位线（WBL）的至少两个存储器单元。每个存储单元耦合到相应的读字线（RWL）和相应的写字线（WWL）。写跟踪控制电路耦合到存储器单元，以确定存储器单元的写入时间。写跟踪控制电路能够接收输入电压并提供输出电压。在写跟踪操作期间，各存储单元的相应RWL和相应的WWL被断言。

9. 发明授权

US08605523B2 Tracking capacitive loads 有权
标题翻译：跟踪容性负载
公开(公告)号：US08605523B2
公开(公告)日：2013-12-10
申请号：US13399877
申请日：2012-02-17
申请人： Derek C. Tao , Young Seog Kim , Kuoyuan (Peter) Hsu , Bing Wang , Annie-Li-Keow Lum
发明人： Derek C. Tao , Young Seog Kim , Kuoyuan (Peter) Hsu , Bing Wang , Annie-Li-Keow Lum
IPC分类号： G11C7/00
CPC分类号： G11C29/24 , G11C7/222 , G11C11/41 , G11C29/50012 , G11C2029/5002
摘要： A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.
摘要翻译：确定时间延迟以覆盖具有跟踪电路的存储器宏中的存储器单元的定时。基于时间延迟，确定与时间延迟相对应的电容。使用具有确定的电容的电容器。电容器耦合到跟踪电路的跟踪单元的第一数据线。第一数据线的第一转变导致存储器单元的第二数据线的第一转变。

10. 发明授权

US08208329B2 No-disturb bit line write for improving speed of eDRAM 有权
标题翻译：无干扰位线写入以提高eDRAM的速度
公开(公告)号：US08208329B2
公开(公告)日：2012-06-26
申请号：US13094389
申请日：2011-04-26
申请人： Subramani Kengeri , Kuoyuan (Peter) Hsu , Bing Wang
发明人： Subramani Kengeri , Kuoyuan (Peter) Hsu , Bing Wang
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C2207/104
摘要： A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit line and a second global bit line coupled to the first and the second local bit lines, respectively. The method further includes starting an equalization to equalize voltages on the first and the second local bit lines; stopping the equalization; and after the step of starting the equalization and before the step of stopping the equalization, writing values from the first and the second global bit lines to the first and the second local bit lines.
摘要翻译：一种操作存储电路的方法包括提供存储电路。存储电路包括存储单元; 连接到存储单元的字线; 连接到存储单元的第一局部位线和第二局部位线; 以及分别耦合到第一和第二局部位线的第一全局位线和第二全局位线。该方法还包括开始均衡以均衡第一和第二局部位线上的电压; 停止均衡并且在开始均衡的步骤之后，在停止均衡的步骤之前，将值从第一和第二全局位线写入第一和第二局部位线。

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