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1. 发明授权

US07810086B2 Safe code-motion of dangerous instructions during compiler optimization 有权
标题翻译：编译器优化过程中危险指令的安全代码运动
公开(公告)号：US07810086B2
公开(公告)日：2010-10-05
申请号：US11172675
申请日：2005-06-30
申请人： Brian R. Murphy , Vijay S. Menon , Tatiana Shpeisman , Ali-Reza Adl-Tabataba , Leaf Petersen
发明人： Brian R. Murphy , Vijay S. Menon , Tatiana Shpeisman , Ali-Reza Adl-Tabataba , Leaf Petersen
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： A compiler can perform aggressive code motion optimization by respecting value dependence of safety values inserted into the intermediate representation of a computer program. In one embodiment, the present invention includes converting a computer program into an intermediate representation, the intermediate representation containing at least one safety check ensuring the safety of at least one dangerous instruction. In one embodiment, the invention further includes defining a safety value in the intermediate representation as the safety check and including the safety value as a safety argument of the dangerous instruction. In one embodiment, it is determined that the safety check is redundant. In response, in one embodiment, the invention includes updating the safety argument of the dangerous instruction, and eliminating the safety check from the intermediate representation during the safety check elimination optimization. Other embodiments are described and claimed.
摘要翻译：编译器可以通过考虑插入到计算机程序的中间表示中的安全值的值依赖性来执行积极的代码运动优化。在一个实施例中，本发明包括将计算机程序转换为中间表示，所述中间表示包含至少一个确保至少一个危险指令的安全性的安全检查。在一个实施例中，本发明还包括将中间表示中的安全值定义为安全检查，并将安全值作为危险指令的安全性参数。在一个实施例中，确定安全检查是多余的。作为响应，在一个实施例中，本发明包括更新危险指令的安全性参数，并且在安全检查消除优化期间从中间表示中消除安全检查。描述和要求保护其他实施例。

2. 发明申请

US20070006187A1 Safe code-motion of dangerous instructions during compiler optimization 有权
标题翻译：编译器优化过程中危险指令的安全代码运动
公开(公告)号：US20070006187A1
公开(公告)日：2007-01-04
申请号：US11172675
申请日：2005-06-30
申请人： Brian Murphy , Vijay Menon , Tatiana Shpeisman , Ali-Reza Adl-Tabataba , Leaf Petersen
发明人： Brian Murphy , Vijay Menon , Tatiana Shpeisman , Ali-Reza Adl-Tabataba , Leaf Petersen
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： A compiler can perform aggressive code motion optimization by respecting value dependence of safety values inserted into the intermediate representation of a computer program. In one embodiment, the present invention includes converting a computer program into an intermediate representation, the intermediate representation containing at least one safety check ensuring the safety of at least one dangerous instruction. In one embodiment, the invention further includes defining a safety value in the intermediate representation as the safety check and including the safety value as a safety argument of the dangerous instruction. In one embodiment, it is determined that the safety check is redundant. In response, in one embodiment, the invention includes updating the safety argument of the dangerous instruction, and eliminating the safety check from the intermediate representation during the safety check elimination optimization. Other embodiments are described and claimed.
摘要翻译：编译器可以通过考虑插入到计算机程序的中间表示中的安全值的值依赖性来执行积极的代码运动优化。在一个实施例中，本发明包括将计算机程序转换为中间表示，所述中间表示包含至少一个确保至少一个危险指令的安全性的安全检查。在一个实施例中，本发明还包括将中间表示中的安全值定义为安全检查，并将安全值作为危险指令的安全性参数。在一个实施例中，确定安全检查是多余的。作为响应，在一个实施例中，本发明包括更新危险指令的安全性参数，并且在安全检查消除优化期间从中间表示中消除安全检查。描述和要求保护其他实施例。

3. 发明申请

US20070006197A1 Safety verification of computer program 审中-公开
标题翻译：计算机程序的安全验证
公开(公告)号：US20070006197A1
公开(公告)日：2007-01-04
申请号：US11172676
申请日：2005-06-30
申请人： Brian Murphy , Vijay Menon , Tatiana Shpeisman , Ali-Reza Adl-Tabataba , Leaf Peterson
发明人： Brian Murphy , Vijay Menon , Tatiana Shpeisman , Ali-Reza Adl-Tabataba , Leaf Peterson
IPC分类号： G06F9/45
CPC分类号： G06F8/43
摘要： Optimized intermediate representation of a computer program can be verified using safety values. In one embodiment, the invention includes receiving an optimized intermediate representation of a computer program, the intermediate representation including a plurality of safety values representing safety dependencies, and verifying the safety of the computer program by checking value dependence between the plurality of safety values. Other embodiments are described and claimed.
摘要翻译：可以使用安全值验证计算机程序的优化中间表示。在一个实施例中，本发明包括接收计算机程序的优化中间表示，所述中间表示包括表示安全依赖性的多个安全值，以及通过检查所述多个安全值之间的值依赖性来验证所述计算机程序的安全性。描述和要求保护其他实施例。

4. 发明申请

US20150100741A1 TRANSACTIONAL MEMORY MANAGEMENT TECHNIQUES 有权
标题翻译：交易记忆管理技术
公开(公告)号：US20150100741A1
公开(公告)日：2015-04-09
申请号：US14129936
申请日：2013-07-15
申请人： Irina Calciu , Justin E. Gottschlich , Tatiana Shpeisman
发明人： Irina Calciu , Justin E. Gottschlich , Tatiana Shpeisman
IPC分类号： G06F9/46
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/067 , G06F3/0673 , G06F9/44 , G06F9/466 , G06F9/467 , G06F12/0813
摘要： Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed.
摘要翻译：描述了改进的事务性内存管理技术。在一个实施例中，例如，设备可以包括处理器元件，用于由处理器元件执行以根据事务存储器进程同时执行软件事务和硬件事务的执行部件，用于由处理器元件执行的跟踪部件激活全局锁以指示软件事务正在执行;以及最终化组件，用于由处理器元件执行以提交软件事务，并且在执行软件事务完成时停用全局锁定，终止组件中止硬件当执行硬件事务完成时，全局锁活动时的事务。描述和要求保护其他实施例。

5. 发明申请

US20140071144A1 METHOD AND APPARATUS TO FACILITATE SHARED POINTERS IN A HETEROGENEOUS PLATFORM 有权
标题翻译：在异位平台上配置共享点的方法和装置
公开(公告)号：US20140071144A1
公开(公告)日：2014-03-13
申请号：US14020616
申请日：2013-09-06
申请人： Yang Ni , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
发明人： Yang Ni , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
IPC分类号： G06T1/60
CPC分类号： G06F12/0806 , G06F15/167 , G06T1/60
摘要： A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.
摘要翻译：一种促进异构平台中的共享指针的方法和装置。在本发明的一个实施例中，异构或非均匀平台包括但不限于中央处理核心或单元，图形处理核心或单元，数字信号处理器，接口模块和任何其他形式的处理核心。异构平台具有促进共享指向CPU和GPU共享的存储器的位置的逻辑。通过在异构平台中共享指针，可以简化异构平台中不同核心之间的数据或信息共享。

6. 发明授权

US08065491B2 Efficient non-transactional write barriers for strong atomicity 有权
标题翻译：有效的非事务性写入障碍，用于强原子性
公开(公告)号：US08065491B2
公开(公告)日：2011-11-22
申请号：US11967232
申请日：2007-12-30
申请人： Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Vijay Menon , Bratin Saha
发明人： Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Vijay Menon , Bratin Saha
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F9/3834 , G06F9/3863 , G06F9/466 , G06F9/52 , G06F9/522 , G06F12/0897 , G06F12/1027
摘要： A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.
摘要翻译：这里描述了用于为非事务写入提供优化的强原子性操作的方法和装置。在初始非事务写入到存储器位置时获取锁定。维护锁，直到检测到事件导致锁的释放。结果，在获取和释放锁之间的中间期，通过不执行锁获取操作来加速对被锁定的存储器位置的任何后续写入。

7. 发明申请

US20110271017A1 EFFICIENT NON-TRANSACTIONAL WRITE BARRIERS FOR STRONG ATOMICITY 有权
标题翻译：有效的非事务性写作障碍强大的原子性
公开(公告)号：US20110271017A1
公开(公告)日：2011-11-03
申请号：US13182162
申请日：2011-07-13
申请人： Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Vijay Menon , Bratin Saha
发明人： Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Vijay Menon , Bratin Saha
IPC分类号： G06F5/14
CPC分类号： G06F12/0804 , G06F9/3834 , G06F9/3863 , G06F9/466 , G06F9/52 , G06F9/522 , G06F12/0897 , G06F12/1027
摘要： A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.
摘要翻译：这里描述了用于为非事务写入提供优化的强原子性操作的方法和装置。在初始非事务写入到存储器位置时获取锁定。维护锁，直到检测到事件导致锁的释放。结果，在获取和释放锁之间的中间期，通过不执行锁获取操作来加速对锁定的存储器位置的任何后续写入。

8. 发明申请

US20100162249A1 OPTIMIZING QUIESCENCE IN A SOFTWARE TRANSACTIONAL MEMORY (STM) SYSTEM 审中-公开
标题翻译：优化软件交易存储器（STM）系统中的优势
公开(公告)号：US20100162249A1
公开(公告)日：2010-06-24
申请号：US12344144
申请日：2008-12-24
申请人： Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Vijay Menon
发明人： Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Vijay Menon
IPC分类号： G06F9/46
CPC分类号： G06F9/466
摘要： A method and apparatus for optimizing quiescence in a transactional memory system is herein described. Non-ordering transactions, such as read-only transactions, transactions that do not access non-transactional data, and write-buffering hardware transactions, are identified. Quiescence in weak atomicity software transactional memory (STM) systems is optimized through selective application of quiescence. As a result, transactions may be decoupled from dependency on quiescing/waiting on previous non-ordering transaction to increase parallelization and reduce inefficiency based on serialization of transactions.
摘要翻译：这里描述了用于优化事务存储器系统中的静止的方法和装置。标识非排序事务，例如只读事务，不访问非事务数据的事务和写缓冲硬件事务。弱原子软件事务存储（STM）系统中的静止通过选择性应用静态来优化。因此，事务可以与依赖于静态/等待以前的非排序事务相关联，以增加并行化并基于事务的序列化降低效率。

9. 发明授权

US07567963B2 Thread synchronization with lock inflation methods and apparatus for managed run-time environments 失效
标题翻译：用于管理运行时环境的锁定充电方法和设备的线程同步
公开(公告)号：US07567963B2
公开(公告)日：2009-07-28
申请号：US10878210
申请日：2004-06-28
申请人： Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Brian Murphy
发明人： Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Brian Murphy
IPC分类号： G06F7/00
CPC分类号： G06F9/528 , G06F9/3004 , G06F9/30087 , G06F9/52 , Y10S707/99938
摘要： Thread synchronization with lock inflation methods and apparatus for managed run-time environments are disclosed. An example method disclosed herein comprises determining a locking operation to perform on a lock corresponding to the object, performing an optimistically balanced synchronization of the lock if the locking operation is not unbalanced, and modifying a lock shape of the lock if the locking operation is unbalanced.
摘要翻译：公开了具有用于管理的运行时环境的锁定充气方法和装置的线程同步。本文公开的示例性方法包括确定对与对象相对应的锁执行的锁定操作，如果锁定操作不是不平衡则执行锁的乐观平衡的同步，以及如果锁定操作不平衡则修改锁的形状。

10. 发明授权

US10210018B2 Optimizing quiescence in a software transactional memory (STM) system 有权
公开(公告)号：US10210018B2
公开(公告)日：2019-02-19
申请号：US12344144
申请日：2008-12-24
申请人： Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Vijay Menon
发明人： Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Vijay Menon
IPC分类号： G06F9/46
摘要： A method and apparatus for optimizing quiescence in a transactional memory system is herein described. Non-ordering transactions, such as read-only transactions, transactions that do not access non-transactional data, and write-buffering hardware transactions, are identified. Quiescence in weak atomicity software transactional memory (STM) systems is optimized through selective application of quiescence. As a result, transactions may be decoupled from dependency on quiescing/waiting on previous non-ordering transaction to increase parallelization and reduce inefficiency based on serialization of transactions.

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