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1. 发明授权

US08654595B2 Nonvolatile memory device with a clamping voltage generation circuit for compensating the variations in memory cell parameters 有权
标题翻译：具有用于补偿存储单元参数变化的钳位电压产生电路的非易失性存储器件
公开(公告)号：US08654595B2
公开(公告)日：2014-02-18
申请号：US13604688
申请日：2012-09-06
申请人： Chan-Kyung Kim , Hong-Sun Hwang , Chul-Woo Park , Sang-Beom Kang , Hyung-Rok Oh
发明人： Chan-Kyung Kim , Hong-Sun Hwang , Chul-Woo Park , Sang-Beom Kang , Hyung-Rok Oh
IPC分类号： G11C7/02
CPC分类号： G11C5/145 , G11C7/12 , G11C11/1673
摘要： A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit.
摘要翻译：非易失性存储器件包括非易失性单元阵列，其包括存储单元和参考单元，钳位电路电连接到存储单元并且被配置为在读取操作期间钳位施加到数据感测线的电压，以及钳位电压产生单元被配置为响应于具有基于参考单元的电平的第一电压产生钳位电压，并且将钳位电压反馈到钳位电路。

2. 发明授权

US08677216B2 Stacked semiconductor memory device and related error-correction method 有权
标题翻译：堆叠式半导体存储器件及相关纠错方法
公开(公告)号：US08677216B2
公开(公告)日：2014-03-18
申请号：US13015850
申请日：2011-01-28
申请人： Chul-Woo Park , Hong-Sun Hwang , Kwan-Young Oh , Sang-Beom Kang
发明人： Chul-Woo Park , Hong-Sun Hwang , Kwan-Young Oh , Sang-Beom Kang
IPC分类号： G11C29/00
CPC分类号： G06F11/1044
摘要： A stacked semiconductor memory device includes an error correction code (ECC) controller that controls the number of bits in an ECC word and corrects errors in memory cell array layers using the ECC word.
摘要翻译：叠层半导体存储器件包括纠错码（ECC）控制器，其控制ECC字中的位数，并使用ECC字来校正存储单元阵列层中的错误。

3. 发明授权

US08780656B2 Stacked memory device and method of repairing same 失效
标题翻译：堆叠式存储器件及其修复方法
公开(公告)号：US08780656B2
公开(公告)日：2014-07-15
申请号：US13015847
申请日：2011-01-28
申请人： Chul-Woo Park , Hong-Sun Hwang , Sang-Beom Kang , Won-Seok Lee
发明人： Chul-Woo Park , Hong-Sun Hwang , Sang-Beom Kang , Won-Seok Lee
IPC分类号： G11C7/00 , G11C5/02
CPC分类号： G11C5/025 , G11C29/80
摘要： A stacked semiconductor memory device comprises memory cell array layers that are stacked in an inverted wedge shape and have different redundancy sizes from each other. The stacked semiconductor memory device has space for vertical connection between layers, a relatively small size, and a relatively high yield.
摘要翻译：层叠的半导体存储器件包括以倒置的楔形堆叠并且具有彼此不同的冗余尺寸的存储单元阵列层。层叠的半导体存储器件具有用于层之间的垂直连接的空间，相对较小的尺寸和相对较高的产量。

4. 发明申请

US20130148429A1 MEMORY DEVICE, METHOD OF PERFORMING READ OR WRITE OPERATION AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：存储器件，执行读或写操作的方法和包括其的存储器系统
公开(公告)号：US20130148429A1
公开(公告)日：2013-06-13
申请号：US13705143
申请日：2012-12-04
申请人： Chan-Kyung Kim , Yun-Sang Lee , Chul-Woo Park , Hong-Sun Hwang
发明人： Chan-Kyung Kim , Yun-Sang Lee , Chul-Woo Park , Hong-Sun Hwang
IPC分类号： G11C7/06 , G11C11/16 , G11C16/26 , G11C13/00
CPC分类号： G11C7/06 , G11C7/065 , G11C7/222 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/4091 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/26 , G11C16/28 , G11C27/02 , G11C2207/002 , G11C2207/005 , G11C2213/71 , H01L27/222 , H01L43/08 , H01L45/04 , H01L45/06
摘要： Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.
摘要翻译：提供了一种存储器件，其具有被配置为接收第一CSL信号以输入或输出数据的第一开关。第二开关被配置为接收第二CSL信号。感测和锁存电路（SLC）耦合在第一和第二开关之间。并且至少一个存储器单元耦合到第二开关。第二开关被配置为响应于第二CSL信号来控制至少一个存储器单元的读取或写入操作的定时，例如，可以在不超过约5ns的范围内执行读取操作。 SLC作为写入模式的锁存器和读取模式下的放大器工作。存储器装置可以包括存储器系统的一部分或包括这种存储器装置或系统的其他装置。还提供了使用这种存储器件执行读和写操作的方法。

5. 发明授权

US09171589B2 Memory device, method of performing read or write operation and memory system including the same 有权
标题翻译：存储器件，执行读或写操作的方法和包括其的存储器系统
公开(公告)号：US09171589B2
公开(公告)日：2015-10-27
申请号：US13705143
申请日：2012-12-04
申请人： Chan-Kyung Kim , Yun-Sang Lee , Chul-Woo Park , Hong-Sun Hwang
发明人： Chan-Kyung Kim , Yun-Sang Lee , Chul-Woo Park , Hong-Sun Hwang
IPC分类号： G11C16/04 , G11C7/06 , G11C13/00 , G11C11/16 , G11C16/26
CPC分类号： G11C7/06 , G11C7/065 , G11C7/222 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/4091 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/26 , G11C16/28 , G11C27/02 , G11C2207/002 , G11C2207/005 , G11C2213/71 , H01L27/222 , H01L43/08 , H01L45/04 , H01L45/06
摘要： Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.
摘要翻译：提供了一种存储器件，其具有被配置为接收第一CSL信号以输入或输出数据的第一开关。第二开关被配置为接收第二CSL信号。感测和锁存电路（SLC）耦合在第一和第二开关之间。并且至少一个存储器单元耦合到第二开关。第二开关被配置为响应于第二CSL信号来控制至少一个存储器单元的读取或写入操作的定时，例如，可以在不超过约5ns的范围内执行读取操作。 SLC作为写入模式的锁存器和读取模式下的放大器工作。存储器装置可以包括存储器系统的一部分或包括这种存储器装置或系统的其他装置。还提供了使用这种存储器件执行读和写操作的方法。

6. 发明授权

US08619458B2 Bidirectional resistive memory devices using selective read voltage polarity 失效
标题翻译：使用选择性读取电压极性的双向电阻式存储器件
公开(公告)号：US08619458B2
公开(公告)日：2013-12-31
申请号：US13349167
申请日：2012-01-12
申请人： In-Gyu Baek , Hyung-Rok Oh , Hong-Sun Hwang
发明人： In-Gyu Baek , Hyung-Rok Oh , Hong-Sun Hwang
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C8/10 , G11C11/16 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007
摘要： A memory device includes a memory cell array including a plurality of memory cells, each including a bidirectional variable resistance element and an input/output circuit configured to determine a polarity for a read voltage to be applied to a selected memory cell among the plurality of memory cells and to apply the read voltage with the determined polarity to the selected memory cell. The input/output circuit may include a polarity determination circuit configured to determine the polarity responsive to a determination mode signal and a driver circuit configured to apply the read voltage with the determined polarity to the selected memory cell.
摘要翻译：存储器件包括存储单元阵列，其包括多个存储器单元，每个存储器单元包括双向可变电阻元件和输入/输出电路，该输入/输出电路被配置为确定要施加到多个存储器中的选定存储单元的读取电压的极性并将所确定的极性的读取电压施加到所选存储单元。输入/输出电路可以包括极性确定电路，其被配置为响应于确定模式信号确定极性，并且驱动器电路被配置为将所确定的极性的读取电压施加到所选存储单元。

7. 发明申请

US20120182786A1 BIDIRECTIONAL RESISTIVE MEMORY DEVICES USING SELECTIVE READ VOLTAGE POLARITY 失效
标题翻译：使用选择性读取电压极性的双向电阻存储器件
公开(公告)号：US20120182786A1
公开(公告)日：2012-07-19
申请号：US13349167
申请日：2012-01-12
申请人： In-Gyu Baek , Hyung-Rok Oh , Hong-Sun Hwang
发明人： In-Gyu Baek , Hyung-Rok Oh , Hong-Sun Hwang
IPC分类号： G11C11/21
CPC分类号： G11C13/004 , G11C8/10 , G11C11/16 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007
摘要： A memory device includes a memory cell array including a plurality of memory cells, each including a bidirectional variable resistance element and an input/output circuit configured to determine a polarity for a read voltage to be applied to a selected memory cell among the plurality of memory cells and to apply the read voltage with the determined polarity to the selected memory cell. The input/output circuit may include a polarity determination circuit configured to determine the polarity responsive to a determination mode signal and a driver circuit configured to apply the read voltage with the determined polarity to the selected memory cell.
摘要翻译：存储器件包括存储单元阵列，其包括多个存储器单元，每个存储器单元包括双向可变电阻元件和输入/输出电路，该输入/输出电路被配置为确定要施加到多个存储器中的选定存储单元的读取电压的极性并将所确定的极性的读取电压施加到所选存储单元。输入/输出电路可以包括极性确定电路，其被配置为响应于确定模式信号确定极性，并且驱动器电路被配置为将所确定的极性的读取电压施加到所选存储单元。

8. 发明授权

US09165637B2 Volatile memory device and a memory controller 有权
标题翻译：易失性存储器件和存储器控制器
公开(公告)号：US09165637B2
公开(公告)日：2015-10-20
申请号：US13720998
申请日：2012-12-19
申请人： Sang-Yun Kim , Jong-Pil Son , Su-A Kim , Chul-Woo Park , Hong-Sun Hwang
发明人： Sang-Yun Kim , Jong-Pil Son , Su-A Kim , Chul-Woo Park , Hong-Sun Hwang
IPC分类号： G11C29/00 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/40611 , G11C11/40618 , G11C11/40622 , G11C11/408 , G11C11/4096 , G11C2211/4061
摘要： A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.
摘要翻译：操作易失性存储器件的方法包括存储弱单元行的地址信息。根据一些示例，在写入弱单元行之后，在预定时间内对弱单元行执行刷新操作。根据一些示例，可以以对正常单元行的写恢复时间更长的写恢复时间来执行对弱单元行的写入操作。

9. 发明授权

US08934311B2 Semiconductor memory device capable of screening a weak bit and repairing the same 有权
标题翻译：半导体存储器能够筛选弱点并进行修复
公开(公告)号：US08934311B2
公开(公告)日：2015-01-13
申请号：US13604308
申请日：2012-09-05
申请人： Hak-soo Yu , Uk-song Kang , Chul-woo Park , Joo-sun Choi , Hong-Sun Hwang
发明人： Hak-soo Yu , Uk-song Kang , Chul-woo Park , Joo-sun Choi , Hong-Sun Hwang
IPC分类号： G11C29/44 , G11C29/50 , G11C29/00 , G11C29/04 , G11C11/41
CPC分类号： G11C29/50 , G11C11/41 , G11C29/783 , G11C2029/0409 , G11C2029/4402
摘要： A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.
摘要翻译：半导体器件包括包括多个存储单元的第一存储区域; 测试单元，被配置为测试所述第一存储器区域，并且从所述多个存储器单元中检测弱位; 以及第二存储器区域，被配置为存储所述第一存储器区域的弱位地址（WBA）以及要存储在所述弱位中的数据，其中所述第一存储器区域和所述第二存储器区域包括不同类型的存储器单元。

10. 发明授权

US08873324B2 Method of refreshing a memory device, refresh address generator and memory device 有权
标题翻译：刷新存储器件，刷新地址发生器和存储器件的方法
公开(公告)号：US08873324B2
公开(公告)日：2014-10-28
申请号：US13240049
申请日：2011-09-22
申请人： Chul-Woo Park , Joo-Sun Choi , Hong-Sun Hwang
发明人： Chul-Woo Park , Joo-Sun Choi , Hong-Sun Hwang
IPC分类号： G11C7/00
CPC分类号： G11C11/40618 , G11C11/40622 , G11C11/408
摘要： A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging.
摘要翻译：生成具有刷新周期的刷新地址，以刷新刷新的存储器件。当刷新地址是第二地址而不是具有第二地址的第一强单元时，对具有第一地址的弱小区执行相应的刷新。当刷新地址是第三地址时，在具有第三地址的第一强单元或第二强单元之一上执行相应的刷新。仅对第一，第二和第三地址中的一个存储地址信息，从而可以减少存储容量。在替代方面，当刷新地址是至少一个预定地址中的任一个以导致刷新利用时，依赖于标志，在弱小区，第一强小区或第二强小区中的一个上执行相应的刷新。

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