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1. 发明授权

US08654595B2 Nonvolatile memory device with a clamping voltage generation circuit for compensating the variations in memory cell parameters 有权
标题翻译：具有用于补偿存储单元参数变化的钳位电压产生电路的非易失性存储器件
公开(公告)号：US08654595B2
公开(公告)日：2014-02-18
申请号：US13604688
申请日：2012-09-06
申请人： Chan-Kyung Kim , Hong-Sun Hwang , Chul-Woo Park , Sang-Beom Kang , Hyung-Rok Oh
发明人： Chan-Kyung Kim , Hong-Sun Hwang , Chul-Woo Park , Sang-Beom Kang , Hyung-Rok Oh
IPC分类号： G11C7/02
CPC分类号： G11C5/145 , G11C7/12 , G11C11/1673
摘要： A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit.
摘要翻译：非易失性存储器件包括非易失性单元阵列，其包括存储单元和参考单元，钳位电路电连接到存储单元并且被配置为在读取操作期间钳位施加到数据感测线的电压，以及钳位电压产生单元被配置为响应于具有基于参考单元的电平的第一电压产生钳位电压，并且将钳位电压反馈到钳位电路。

2. 发明授权

US09183910B2 Semiconductor memory devices for alternately selecting bit lines 有权
标题翻译：用于交替选择位线的半导体存储器件
公开(公告)号：US09183910B2
公开(公告)日：2015-11-10
申请号：US13907223
申请日：2013-05-31
申请人： Yun-Sang Lee , Dong-Seok Kang , Sang-Beom Kang , Chan-Kyung Kim , Chul-Woo Park , Dong-Hyun Sohn , Hyung-Rok Oh
发明人： Yun-Sang Lee , Dong-Seok Kang , Sang-Beom Kang , Chan-Kyung Kim , Chul-Woo Park , Dong-Hyun Sohn , Hyung-Rok Oh
IPC分类号： G11C11/16 , G11C7/12
CPC分类号： G11C11/1653 , G11C7/12 , G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/1697
摘要： A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).
摘要翻译：半导体存储器件包括一个单元阵列，其包括一个或多个存储体组，其中一个或多个存储体组中的每个组包括多个存储体，并且多个存储体中的每一个存储体包括多个自旋传递转矩磁阻随机存取存储器（STT -MRAM）细胞。半导体存储器件还包括用于向连接到多个STT-MRAM单元中的每一个的源极线施加电压的源极电压产生单元，以及用于对来自外部源的命令进行解码的命令解码器，以执行读取和对多个STT-MRAM单元进行写入操作。该命令包括行地址选通（RAS），列地址选通（CAS），片选信号（CS），写使能信号（WE）和时钟使能信号（CKE）的至少一个信号）。

3. 发明授权

US07903448B2 Resistance random access memory having common source line 有权
标题翻译：具有共同源极线的电阻随机存取存储器
公开(公告)号：US07903448B2
公开(公告)日：2011-03-08
申请号：US11964142
申请日：2007-12-26
申请人： Hyung-Rok Oh , Sang-Beom Kang , Joon-Min Park , Woo-Yeong Cho
发明人： Hyung-Rok Oh , Sang-Beom Kang , Joon-Min Park , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/31 , G11C2213/79
摘要： A resistance random access memory (RRAM) having a source line shared structure and an associated data access method. The RRAM, in which a write operation of writing data of first state and second state to a selected memory cell is performed through first and second write paths having mutually opposite directions, includes word lines, bit lines, a memory cell array and a plurality of source lines. The memory cell array includes a plurality of memory cells each constructed of an access transistor coupled to a resistive memory device. The memory cells are disposed in a matrix of rows and columns and located at each intersection of a word line and a bit line. Each of the plurality of source lines is disposed between a pair of word lines and in the same direction as the word lines. A positive voltage is applied to a source line in a memory cell write operation. Through the source line shared structure, occupied chip area is reduced and, in a write operating mode, a bit line potential can be determined within a positive voltage level range.
摘要翻译：具有源线共享结构的电阻随机存取存储器（RRAM）和相关联的数据存取方法。其中通过具有相互相反方向的第一和第二写入路径来执行将第一状态和第二状态的数据写入所选存储单元的写入操作，包括字线，位线，存储单元阵列和多个源线。存储单元阵列包括多个存储单元，每个存储单元由耦合到电阻存储器件的存取晶体管构成。存储单元被布置成行和列的矩阵并且位于字线和位线的每个交叉点处。多个源极线中的每一个被设置在一对字线之间并且在与字线相同的方向上。在存储单元写入操作中，将正电压施加到源极线。通过源极线共享结构，占用的芯片面积减小，并且在写入操作模式中，可以在正电压电平范围内确定位线电位。

4. 发明授权

US07542356B2 Semiconductor memory device and method for reducing cell activation during write operations 有权
标题翻译：用于在写入操作期间减少电池激活的半导体存储器件和方法
公开(公告)号：US07542356B2
公开(公告)日：2009-06-02
申请号：US11790146
申请日：2007-04-24
申请人： Kwang-Jin Lee , Sang-Beom Kang , Hyung-Rok Oh , Beak-Hyung Cho , Woo-Yeong Cho
发明人： Kwang-Jin Lee , Sang-Beom Kang , Hyung-Rok Oh , Beak-Hyung Cho , Woo-Yeong Cho
IPC分类号： G11C7/06
CPC分类号： G11C13/0069 , G11C7/06 , G11C7/1006 , G11C13/0004 , G11C2013/0076 , G11C2211/5647
摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.
摘要翻译：本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。

5. 发明授权

US07710767B2 Memory cell array biasing method and a semiconductor memory device 有权
标题翻译：存储单元阵列偏置方法和半导体存储器件
公开(公告)号：US07710767B2
公开(公告)日：2010-05-04
申请号：US11969326
申请日：2008-01-04
申请人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译：一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件，其中半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多个第一行中的对应的第一行和存储单元的第二端连接到多条第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

6. 发明授权

US07993961B2 Layout structure in semiconductor memory device comprising global word lines, local word lines, global bit lines and local bit lines 有权
标题翻译：包括全局字线，局部字线，全局位线和局部位线的半导体存储器件中的布局结构
公开(公告)号：US07993961B2
公开(公告)日：2011-08-09
申请号：US12509617
申请日：2009-07-27
申请人： Hyung-Rok Oh , Sang-Beom Kang , Du-Eung Kim
发明人： Hyung-Rok Oh , Sang-Beom Kang , Du-Eung Kim
IPC分类号： H01L21/06
CPC分类号： G11C7/18 , G11C5/063 , G11C13/0004 , G11C2213/72 , H01L27/24
摘要： A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.
摘要翻译：提供了具有层次结构的半导体存储器件中的线路布局结构和方法。在具有全局字线和本地字线以及全局位线和局部位线的半导体存储器件中，并且单独地布置全局全局字线，局部字线，全局位线和局部位在至少三层中的导电层上线; 全局字线，本地字线，全局位线和局部位线中的至少两个在一个导电层上一并设置。构成半导体存储器件的信号线以分层结构设置，从而可以获得有利地具有高集成度，高速度和高性能的半导体存储器件。

7. 发明授权

US07907467B2 Resistance semiconductor memory device having three-dimensional stack and word line decoding method thereof 有权
标题翻译：具有三维堆叠和字线解码方法的电阻半导体存储器件
公开(公告)号：US07907467B2
公开(公告)日：2011-03-15
申请号：US12873836
申请日：2010-09-01
申请人： Joon-Min Park , Sang-Beom Kang , Hyung-Rok Oh , Woo-Yeong Cho
发明人： Joon-Min Park , Sang-Beom Kang , Hyung-Rok Oh , Woo-Yeong Cho
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C8/14 , G11C11/16 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/71 , G11C2213/72
摘要： A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved.
摘要翻译：提供三维堆栈结构的电阻半导体存储器件及其字线解码方法。在三维堆叠结构的电阻半导体存储器件中，其中多个字线层和多个位线层交替和垂直地布置，并且其中多个存储单元层设置在字线层和位线层; 电阻半导体存储器件包括沿着第一方向设置在每个位线层上的多个位线作为长度方向; 在与第一方向相交的长度方向的第二方向上设置在每个字线层上的多个子字线; 设置在所述存储单元层上的多个存储单元; 以及多个主字线分别设置在主字线层上，特别适用于位线层和字线层，在第二方向上作为长度方向，多个主字线中的每一条由预定数量的子字线。可以实现足够高集成度的有效的字线解码。

8. 发明申请

US20100329070A1 Resistance Semiconductor Memory Device Having Three-Dimensional Stack and Word Line Decoding Method Thereof 有权
标题翻译：具有三维堆栈和字线解码方法的电阻半导体存储器件
公开(公告)号：US20100329070A1
公开(公告)日：2010-12-30
申请号：US12873836
申请日：2010-09-01
申请人： Joon Min Park , Sang-Beom Kang , Hyung-Rok Oh , Woo-Yeong Cho
发明人： Joon Min Park , Sang-Beom Kang , Hyung-Rok Oh , Woo-Yeong Cho
IPC分类号： G11C8/10
CPC分类号： G11C8/08 , G11C8/14 , G11C11/16 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/71 , G11C2213/72
摘要： A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved.
摘要翻译：提供三维堆栈结构的电阻半导体存储器件及其字线解码方法。在三维堆叠结构的电阻半导体存储器件中，其中多个字线层和多个位线层交替和垂直地布置，并且其中多个存储单元层设置在字线层和位线层; 电阻半导体存储器件包括沿着第一方向设置在每个位线层上的多个位线作为长度方向; 在与第一方向相交的长度方向的第二方向上配置在每个字线层上的多个子字线; 设置在所述存储单元层上的多个存储单元; 以及多个主字线分别设置在主字线层上，特别适用于位线层和字线层，在第二方向上作为长度方向，多个主字线中的每一条由预定数量的子字线。可以实现足够高集成度的有效的字线解码。

9. 发明授权

US07724560B2 Nonvolatile memory device having twin memory cells 有权
标题翻译：具有双存储单元的非易失性存储器件
公开(公告)号：US07724560B2
公开(公告)日：2010-05-25
申请号：US12107985
申请日：2008-04-23
申请人： Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh , Joon-Min Park
发明人： Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh , Joon-Min Park
IPC分类号： G11C5/06
CPC分类号： G11C13/003 , G11C11/14 , G11C11/22 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76
摘要： A nonvolatile memory device includes multiple first bit lines extending in a first direction, multiple word lines formed on the first bit lines and extending in a second direction different from the first direction, and multiple second bit lines, formed on the word lines and extending in the first direction. The nonvoliative memory device also includes multiple twin memory cells, each of which includes a first memory cell coupled between a first bit line and a word line and a second memory cell coupled between the word line and a second bit line. The first and second memory cells store different data.
摘要翻译：非易失性存储器件包括沿第一方向延伸的多个第一位线，形成在第一位线上并在与第一方向不同的第二方向上延伸的多个字线以及形成在字线上并在字线上延伸的多个第二位线第一个方向。非易失性存储器件还包括多个双存储器单元，每个存储单元包括耦合在第一位线和字线之间的第一存储器单元和耦合在字线和第二位线之间的第二存储单元。第一和第二存储单元存储不同的数据。

10. 发明申请

US20080101131A1 Semiconductor memory device and method for reducing cell activation during write operations 有权
标题翻译：用于在写入操作期间减少电池激活的半导体存储器件和方法
公开(公告)号：US20080101131A1
公开(公告)日：2008-05-01
申请号：US11790146
申请日：2007-04-24
申请人： Kwang-Jin Lee , Sang-Beom Kang , Hyung-Rok Oh , Beak-Hyung Cho , Woo-Yeong Cho
发明人： Kwang-Jin Lee , Sang-Beom Kang , Hyung-Rok Oh , Beak-Hyung Cho , Woo-Yeong Cho
IPC分类号： G11C7/06
CPC分类号： G11C13/0069 , G11C7/06 , G11C7/1006 , G11C13/0004 , G11C2013/0076 , G11C2211/5647
摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.
摘要翻译：本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。

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