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1. 发明授权

US08274517B2 Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权
标题翻译：将算法元素下载到协处理器的系统和方法以及相应的技术
公开(公告)号：US08274517B2
公开(公告)日：2012-09-25
申请号：US10986586
申请日：2004-11-12
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
IPC分类号： G06T1/00 , G06T15/00
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译：提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。本发明允许对下载到协处理器的程序的运行时预测流控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。

2. 发明授权

US08035646B2 Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权
标题翻译：将算法元素下载到协处理器的系统和方法以及相应的技术
公开(公告)号：US08035646B2
公开(公告)日：2011-10-11
申请号：US10987120
申请日：2004-11-12
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
IPC分类号： G06T1/00
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译：提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。

3. 发明授权

US08823718B2 Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权
标题翻译：将算法元素下载到协处理器的系统和方法以及相应的技术
公开(公告)号：US08823718B2
公开(公告)日：2014-09-02
申请号：US10987686
申请日：2004-11-12
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
IPC分类号： G06T1/00 , G09G5/36 , G06F9/32 , G06T15/80 , G06F9/38 , G06T15/00
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译：提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。

4. 发明授权

US08305381B2 Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权
标题翻译：将算法元素下载到协处理器的系统和方法以及相应的技术
公开(公告)号：US08305381B2
公开(公告)日：2012-11-06
申请号：US12112676
申请日：2008-04-30
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
IPC分类号： G06T1/00 , G06F13/14 , G09G5/00
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译：提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在顶点着色器提供输入到顶点着色器的顶点着色器的分频，其中可选地支持流模数值，在像素着色器上提供寄存器存储元件，并且与表示像素的面相关联的存储相关联的接口，提供顶点着色器和具有更多片上寄存器存储的像素着色器，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。

5. 发明授权

US07978197B2 Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权
公开(公告)号：US07978197B2
公开(公告)日：2011-07-12
申请号：US10987144
申请日：2004-11-12
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
IPC分类号： G06T1/20 , G06F15/76
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.

6. 发明申请

US20080198169A1 SYSTEMS AND METHODS FOR DOWNLOADING ALGORITHMIC ELEMENTS TO A COPROCESSOR AND CORRESPONDING TECHNIQUES 有权
标题翻译：将算法元素下载到协处理器和相应技术的系统和方法
公开(公告)号：US20080198169A1
公开(公告)日：2008-08-21
申请号：US12112676
申请日：2008-04-30
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
IPC分类号： G06T1/00
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译：提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。

7. 发明申请

US20090256849A1 Systems and Methods for Providing Intermediate Targets in a Graphics System 有权
标题翻译：在图形系统中提供中间目标的系统和方法
公开(公告)号：US20090256849A1
公开(公告)日：2009-10-15
申请号：US12489316
申请日：2009-06-22
申请人： Michele B. Boland , Charles N. Boyd , Anantha R. Kancherla
发明人： Michele B. Boland , Charles N. Boyd , Anantha R. Kancherla
IPC分类号： G06T1/00
CPC分类号： G06T1/60 , G06T15/005
摘要： Systems and methods for utilizing intermediate target(s) in connection with computer graphics in a computer system are provided. In various embodiments, intermediate memory buffers in video memory are provided and utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i.e., the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times as may be desired, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modern graphics chips.
摘要翻译：提供了一种在计算机系统中利用与计算机图形相关的中间目标的系统和方法。在各种实施例中，视频存储器中的中间存储器缓冲器被提供并用于允许来自图形API的序列化程序支持超过单个程序的程序着色器的指令限制的算法。中间缓冲器也可以允许在用于其它目的的程序之间共享数据，并且是原子上可访问的。缓冲器的大小，即存储在中间目标中的数据量可以相对于图形数据可变地设置为分辨率的变化量。在这方面，单个程序产生中间数据，然后可以通过相同程序和/或任何数量的其他程序的扩展来使用和重新使用任何次数的可能的期望，从而实现相当大的灵活性，遮蔽程序的复杂性，同时保持现代图形芯片的速度。

8. 发明申请

US20120113118A1 Systems and Methods for Providing Intermediate Targets in a Graphics System 有权
标题翻译：在图形系统中提供中间目标的系统和方法
公开(公告)号：US20120113118A1
公开(公告)日：2012-05-10
申请号：US13286054
申请日：2011-10-31
申请人： Michele B. Boland , Charles N. Boyd , Anantha R. Kancherla
发明人： Michele B. Boland , Charles N. Boyd , Anantha R. Kancherla
IPC分类号： G06T15/80
CPC分类号： G06T1/60 , G06T15/005
摘要： Utilizing intermediate target(s) in connection with computer graphics in a computer system is provided. In various embodiments, intermediate memory buffers in video memory are provided and utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times as may be desired, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modern graphics chips.
摘要翻译：提供了与计算机系统中的计算机图形相关联的中间目标。在各种实施例中，视频存储器中的中间存储器缓冲器被提供并用于允许来自图形API的序列化程序支持超过单个程序的程序着色器的指令限制的算法。中间缓冲器也可以允许在用于其它目的的程序之间共享数据，并且是原子上可访问的。缓冲器的大小可以相对于图形数据变化地设定为分辨率的变化。在这方面，单个程序产生中间数据，然后可以通过相同程序和/或任何数量的其他程序的扩展来使用和重新使用任何次数的可能的期望，从而实现相当大的灵活性，遮蔽程序的复杂性，同时保持现代图形芯片的速度。

9. 发明授权

US07564460B2 Systems and methods for providing intermediate targets in a graphics system 有权
标题翻译：在图形系统中提供中间目标的系统和方法
公开(公告)号：US07564460B2
公开(公告)日：2009-07-21
申请号：US10196864
申请日：2002-07-16
申请人： Michele B. Boland , Charles N. Boyd , Anantha R. Kancherla
发明人： Michele B. Boland , Charles N. Boyd , Anantha R. Kancherla
IPC分类号： G06F15/80
CPC分类号： G06T1/60 , G06T15/005
摘要： Systems and methods for utilizing intermediate target(s) in connection with computer graphics in a computer system are provided. In various embodiments, intermediate memory buffers in video memory are provided and utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i.e., the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times as may be desired, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modem graphics chips.
摘要翻译：提供了一种在计算机系统中利用与计算机图形相关的中间目标的系统和方法。在各种实施例中，视频存储器中的中间存储器缓冲器被提供并用于允许来自图形API的序列化程序支持超过单个程序的程序着色器的指令限制的算法。中间缓冲器也可以允许在用于其它目的的程序之间共享数据，并且是原子上可访问的。缓冲器的大小，即存储在中间目标中的数据量可以相对于图形数据可变地设置为分辨率的变化量。在这方面，单个程序产生中间数据，然后可以通过相同程序和/或任何数量的其他程序的扩展来使用和重新使用任何次数的可能的期望，从而实现相当大的灵活性，遮蔽程序的复杂性，同时保持调制解调器图形芯片的速度。

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