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1. 发明授权

US08274517B2 Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权
标题翻译：将算法元素下载到协处理器的系统和方法以及相应的技术
公开(公告)号：US08274517B2
公开(公告)日：2012-09-25
申请号：US10986586
申请日：2004-11-12
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
IPC分类号： G06T1/00 , G06T15/00
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译：提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。本发明允许对下载到协处理器的程序的运行时预测流控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。

2. 发明授权

US07978197B2 Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权
公开(公告)号：US07978197B2
公开(公告)日：2011-07-12
申请号：US10987144
申请日：2004-11-12
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
IPC分类号： G06T1/20 , G06F15/76
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.

3. 发明申请

US20080198169A1 SYSTEMS AND METHODS FOR DOWNLOADING ALGORITHMIC ELEMENTS TO A COPROCESSOR AND CORRESPONDING TECHNIQUES 有权
标题翻译：将算法元素下载到协处理器和相应技术的系统和方法
公开(公告)号：US20080198169A1
公开(公告)日：2008-08-21
申请号：US12112676
申请日：2008-04-30
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
IPC分类号： G06T1/00
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译：提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。

4. 发明授权

US08823718B2 Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权
标题翻译：将算法元素下载到协处理器的系统和方法以及相应的技术
公开(公告)号：US08823718B2
公开(公告)日：2014-09-02
申请号：US10987686
申请日：2004-11-12
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
IPC分类号： G06T1/00 , G09G5/36 , G06F9/32 , G06T15/80 , G06F9/38 , G06T15/00
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译：提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。

5. 发明授权

US08305381B2 Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权
标题翻译：将算法元素下载到协处理器的系统和方法以及相应的技术
公开(公告)号：US08305381B2
公开(公告)日：2012-11-06
申请号：US12112676
申请日：2008-04-30
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
IPC分类号： G06T1/00 , G06F13/14 , G09G5/00
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译：提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在顶点着色器提供输入到顶点着色器的顶点着色器的分频，其中可选地支持流模数值，在像素着色器上提供寄存器存储元件，并且与表示像素的面相关联的存储相关联的接口，提供顶点着色器和具有更多片上寄存器存储的像素着色器，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。

6. 发明授权

US08035646B2 Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权
标题翻译：将算法元素下载到协处理器的系统和方法以及相应的技术
公开(公告)号：US08035646B2
公开(公告)日：2011-10-11
申请号：US10987120
申请日：2004-11-12
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
IPC分类号： G06T1/00
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译：提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。

7. 发明申请

US20120278712A1 MULTI-INPUT GESTURES IN HIERARCHICAL REGIONS 审中-公开
标题翻译：分层区域的多重输入
公开(公告)号：US20120278712A1
公开(公告)日：2012-11-01
申请号：US13095495
申请日：2011-04-27
申请人： Stephen H. Wright , Amish Patel , Paul Armistead Hoover , Nicholas R. Waggoner , Michael J. Patten
发明人： Stephen H. Wright , Amish Patel , Paul Armistead Hoover , Nicholas R. Waggoner , Michael J. Patten
IPC分类号： G06F3/041 , G06F3/01
CPC分类号： G06F3/04883 , G06F2203/04803 , G06F2203/04808
摘要： This document describes techniques and apparatuses for multi-input gestures in hierarchical regions. These techniques enable applications to appropriately respond to a multi-input gesture made to one or more hierarchically related regions of an application interface.
摘要翻译：本文档描述了分层区域中多输入手势的技术和装置。这些技术使得应用能够适当地响应对应用接口的一个或多个分层相关区域进行的多输入手势。

8. 发明授权

US08001483B2 Selective display of cursor 有权
标题翻译：选择性显示光标
公开(公告)号：US08001483B2
公开(公告)日：2011-08-16
申请号：US11706621
申请日：2007-02-13
申请人： Jeremy de Souza , Mohamed Sadek , Pravin Kumar Santiago , Stephen H. Wright
发明人： Jeremy de Souza , Mohamed Sadek , Pravin Kumar Santiago , Stephen H. Wright
IPC分类号： G06F3/048
CPC分类号： G06F3/0481 , G09G5/08
摘要： An application may be provided with an interface for hiding a cursor from or showing a cursor to a video driver and for causing cursor information to be saved in data storage and retrieved from data storage. The interface may include an application program interface (API), which may be callable from the application program. The interface may also include one or more bits included in a video driver, such that the modification of any of the one or more bits may change operation of the video driver. Modification of at least some of the bits may cause a cursor to be hidden from the video driver, may cause a previously hidden cursor to be shown to the video driver, may cause cursor information to be saved in a data storage, or may cause the cursor information to be retrieved from the data storage.
摘要翻译：应用程序可以设置有用于将光标隐藏或显示光标到视频驱动器并且用于使光标信息被保存在数据存储器中并从数据存储器检索的接口。接口可以包括可以从应用程序调用的应用程序接口（API）。接口还可以包括包括在视频驱动器中的一个或多个比特，使得一个或多个比特中的任一个的修改可以改变视频驱动器的操作。至少一些位的修改可能导致光标从视频驱动器被隐藏，可能导致先前隐藏的光标被显示给视频驱动器，可能导致光标信息被保存在数据存储器中，或者可能导致要从数据存储中检索的游标信息。

9. 发明授权

US07689926B2 Selective window exclusion for captured content 有权
标题翻译：捕获内容的选择性窗口排除
公开(公告)号：US07689926B2
公开(公告)日：2010-03-30
申请号：US11395077
申请日：2006-03-31
申请人： Jeremy de Souza , Pravin K. Santiago , Stephen H. Wright
发明人： Jeremy de Souza , Pravin K. Santiago , Stephen H. Wright
IPC分类号： G06F3/048
CPC分类号： G06F3/0481
摘要： Described is the selective exclusion of content returned in a requested screen capture operation, wherein exclusion may be determined by a window category and the requesting application program. For example, a magnification program will not received content captured from its own layered window or from any other layered magnification windows. A registration mechanism obtains and maintains a window handle for any window registered for exclusion. A screen capture mechanism uses the information to determine whether to exclude the content of windows when returning the captured screen content. Exclusion may be accomplished by enumerating areas that are not covered by any layered window and copying those areas to a screen representation buffer or the like, and separately enumerating areas that are covered by at least one layered window. A covered area is only copied to the screen representation when it does not correspond to an excluded window.
摘要翻译：描述了在请求的屏幕捕获操作中返回的内容的选择性排除，其中排除可以由窗口类别和请求应用程序确定。例如，放大程序将不会收到从其自己的分层窗口或任何其他分层放大窗口捕获的内容。注册机制获得并维护注册排除的任何窗口的窗口句柄。屏幕捕获机制使用该信息来确定在返回捕获的屏幕内容时是否排除Windows的内容。排除可以通过枚举未被任何分层窗口覆盖的区域并将这些区域复制到屏幕表示缓冲区等来实现，并且分别列举由至少一个分层窗口覆盖的区域。覆盖区域仅在不对应于排除窗口时才复制到屏幕表示。

10. 发明授权

US07619622B2 Selective rendering for driver classes 有权
标题翻译：驱动程序类的选择性渲染
公开(公告)号：US07619622B2
公开(公告)日：2009-11-17
申请号：US11395684
申请日：2006-03-31
申请人： Jeremy de Souza , Pravin K. Santiago , Stephen H. Wright
发明人： Jeremy de Souza , Pravin K. Santiago , Stephen H. Wright
IPC分类号： G06F17/00 , G06F15/16 , G06T1/00 , G09G5/00 , G06K9/62 , G06K9/40 , G06F3/048
CPC分类号： G06T11/20
摘要： Described is a filtering mechanism/process that selectively controls whether graphics primitives are provided to a given driver. For example, graphics primitives of an accessibility (e.g., magnification) program may be excluded from being obtained by mirror drivers associated with the accessibility programs, so that the mirror drivers receive only the primitives of unmagnified windows. A registration mechanism allows a program to identify its window as being associated with a class of drivers for filtering, and the drivers may identify themselves as being of the class. By maintaining data that associates windows with a class of drivers, when graphics primitives associated with a registered window are received, a filtering operation be activated to determine which graphics primitives are provided to which driver or drivers. Filtering may be by exclusion to prevent certain primitives from being obtained by excluded drivers, or by inclusion whereby only included drivers receive certain primitives.
摘要翻译：描述了一种过滤机制/过程，其选择性地控制图形基元是否被提供给给定的驱动器。例如，可访问性（例如，放大）程序的图形基元可以被排除在与可访问性程序相关联的镜像驱动器获得之外，从而镜像驱动程序仅接收非扩展窗口的图元。注册机制允许程序将其窗口识别为与一类用于过滤的驱动程序相关联，并且驱动程序可以将自身标识为类。通过维护将Windows与一类驱动程序相关联的数据，当接收与注册窗口相关联的图形基元时，将激活过滤操作，以确定哪些图形基元提供给哪个驱动程序或驱动程序。可以通过排除来过滤以防止被排除的驱动程序获得某些原语，或者通过包含其中仅包括的驱动程序接收某些原语。

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