专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08338945B2 Molded chip interposer structure and methods 有权
标题翻译：模芯插片架结构及方法
公开(公告)号：US08338945B2
公开(公告)日：2012-12-25
申请号：US12953130
申请日：2010-11-23
申请人： Chen-Hua Yu , Chun Hui Yu , Jing-Cheng Lin
发明人： Chen-Hua Yu , Chun Hui Yu , Jing-Cheng Lin
IPC分类号： H01L23/48
CPC分类号： H01L25/0655 , H01L21/563 , H01L21/568 , H01L23/3157 , H01L23/36 , H01L23/42 , H01L23/49822 , H01L23/49827 , H01L24/81 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00011 , H01L2924/01029 , H01L2924/01322 , H01L2924/09701 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2224/81 , H01L2224/83 , H01L2224/81805
摘要： Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed.
摘要翻译：用于提供模制芯片插入件结构和组装的装置和方法。提供具有设置在模具化合物内的至少两个集成电路管芯的模制芯片结构，其具有底表面上的管芯接合焊盘; 并且在底表面上的电介质层的开口中形成焊料凸块，焊料凸块形成与焊盘的连接。具有裸片侧表面和电路板侧表面的插入件设置有凸起焊盘，其在插入件的裸片侧接收模制芯片结构的焊料凸块。在插入件的裸片侧和围绕焊料凸块的模制芯片结构的底表面之间形成底部填充层。公开了用于形成模制芯片内插器结构的方法。

2. 发明申请

US20120098123A1 Molded Chip Interposer Structure and Methods 有权
标题翻译：成型芯片内插器结构与方法
公开(公告)号：US20120098123A1
公开(公告)日：2012-04-26
申请号：US12953130
申请日：2010-11-23
申请人： Chen-Hua Yu , Chun Hui Yu , Jing-Cheng Lin
发明人： Chen-Hua Yu , Chun Hui Yu , Jing-Cheng Lin
IPC分类号： H01L23/498
CPC分类号： H01L25/0655 , H01L21/563 , H01L21/568 , H01L23/3157 , H01L23/36 , H01L23/42 , H01L23/49822 , H01L23/49827 , H01L24/81 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00011 , H01L2924/01029 , H01L2924/01322 , H01L2924/09701 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2224/81 , H01L2224/83 , H01L2224/81805
摘要： Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed.
摘要翻译：用于提供模制芯片插入件结构和组装的装置和方法。提供具有设置在模具化合物内的至少两个集成电路管芯的模制芯片结构，其具有底表面上的管芯接合焊盘; 并且在底表面上的电介质层的开口中形成焊料凸块，焊料凸块形成与焊盘的连接。具有裸片侧表面和电路板侧表面的插入件设置有凸起焊盘，其在插入件的裸片侧接收模制芯片结构的焊料凸块。在插入件的裸片侧和围绕焊料凸块的模制芯片结构的底表面之间形成底部填充层。公开了用于形成模制芯片内插器结构的方法。

3. 发明授权

US08754514B2 Multi-chip wafer level package 有权
标题翻译：多芯片晶圆级封装
公开(公告)号：US08754514B2
公开(公告)日：2014-06-17
申请号：US13206694
申请日：2011-08-10
申请人： Chun Hui Yu , Chih-Hang Tung , Tung-Liang Shao , Chen-Hua Yu , Da-Yuan Shih
发明人： Chun Hui Yu , Chih-Hang Tung , Tung-Liang Shao , Chen-Hua Yu , Da-Yuan Shih
IPC分类号： H01L23/02 , H01L21/00 , H01L23/48 , H01L23/522 , H01L23/538 , H01L23/00 , H01L21/768 , H01L25/065
CPC分类号： H01L23/481 , H01L21/563 , H01L21/568 , H01L21/76805 , H01L21/76838 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/5226 , H01L23/5389 , H01L24/16 , H01L24/19 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/19 , H01L2224/32145 , H01L2224/32245 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/8203 , H01L2224/94 , H01L2225/06513 , H01L2225/06524 , H01L2225/06548 , H01L2225/06568 , H01L2924/01029 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/18162 , H01L2924/351 , H01L2924/00 , H01L2224/03 , H01L2224/83005
摘要： A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.
摘要翻译：多芯片晶片级封装包括三个堆叠的半导体管芯。第一半导体管芯被嵌入在第一光敏材料层中。第二半导体管芯堆叠在第一半导体管芯的顶部上，其中第二半导体管芯与第一半导体管芯面对面连接。第三半导体管芯背靠背连接到第二半导体管芯。第二半导体管芯和第三半导体管芯都嵌入第二光敏材料层。多芯片晶片级封装还包括形成在第一光敏材料层和第二光敏材料层中的多个通过组装通孔。

4. 发明授权

US09583365B2 Method of forming interconnects for three dimensional integrated circuit 有权
标题翻译：形成三维集成电路互连的方法
公开(公告)号：US09583365B2
公开(公告)日：2017-02-28
申请号：US13481517
申请日：2012-05-25
申请人： Chun Hui Yu , Kuo-Chung Yee , Chen-Hua Yu , Yeong-Jyh Lin , Chia-Hsiang Lin , Liang-Ju Yen , Lawrence Chiang Sheu
发明人： Chun Hui Yu , Kuo-Chung Yee , Chen-Hua Yu , Yeong-Jyh Lin , Chia-Hsiang Lin , Liang-Ju Yen , Lawrence Chiang Sheu
IPC分类号： H01L21/48 , H01L23/498
CPC分类号： H01L21/486 , H01L23/49816 , H01L23/49827 , H01L2224/13099 , H01L2224/16238 , H01L2924/15311 , H01L2924/00014
摘要： A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.
摘要翻译：形成用于三维集成电路的互连的方法包括将金属层附接在第一载体上，将包装部件的第一侧附着在金属层上，其中该封装部件包括多个通孔。该方法还包括使用电化学电镀工艺用金属材料填充多个通孔，其中金属层用作用于电化学电镀工艺的电极，将第二载体附着在包装部件的第二侧上，将第一载体，在金属层上形成光致抗蚀剂层，图案化光致抗蚀剂层并分离金属层的暴露部分。

5. 发明申请

US20130313121A1 Method of Forming Interconnects for Three Dimensional Integrated Circuit 有权
标题翻译：形成三维集成电路互连的方法
公开(公告)号：US20130313121A1
公开(公告)日：2013-11-28
申请号：US13481517
申请日：2012-05-25
申请人： Chun Hui Yu , Kuo-Chung Yee , Chen-Hua Yu , Yeong-Jyh Lin , Chia-Hsiang Lin , Liang-Ju Yen , Lawrence Chiang Sheu
发明人： Chun Hui Yu , Kuo-Chung Yee , Chen-Hua Yu , Yeong-Jyh Lin , Chia-Hsiang Lin , Liang-Ju Yen , Lawrence Chiang Sheu
IPC分类号： C25D5/02 , C25D7/12 , C25D7/00
CPC分类号： H01L21/486 , H01L23/49816 , H01L23/49827 , H01L2224/13099 , H01L2224/16238 , H01L2924/15311 , H01L2924/00014
摘要： A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.
摘要翻译：形成用于三维集成电路的互连的方法包括将金属层附接在第一载体上，将包装部件的第一侧附着在金属层上，其中该封装部件包括多个通孔。该方法还包括使用电化学电镀工艺用金属材料填充多个通孔，其中金属层用作用于电化学电镀工艺的电极，将第二载体附着在包装部件的第二侧上，将第一载体，在金属层上形成光致抗蚀剂层，图案化光致抗蚀剂层并分离金属层的暴露部分。

6. 发明申请

US20130040423A1 Method of Multi-Chip Wafer Level Packaging 审中-公开
标题翻译：多芯片晶圆级封装方法
公开(公告)号：US20130040423A1
公开(公告)日：2013-02-14
申请号：US13206602
申请日：2011-08-10
申请人： Chih-Hang Tung , Chun Hui Yu , Chen-Hua Yu , Da-Yuan Shih
发明人： Chih-Hang Tung , Chun Hui Yu , Chen-Hua Yu , Da-Yuan Shih
IPC分类号： H01L21/56 , H01L21/82
CPC分类号： H01L25/50 , H01L21/4882 , H01L21/561 , H01L21/563 , H01L21/76879 , H01L21/78 , H01L23/3114 , H01L24/03 , H01L24/09 , H01L24/11 , H01L24/17 , H01L24/19 , H01L24/24 , H01L24/27 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L2224/02311 , H01L2224/02381 , H01L2224/0346 , H01L2224/0401 , H01L2224/04105 , H01L2224/05572 , H01L2224/08146 , H01L2224/12105 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73217 , H01L2224/73267 , H01L2224/8203 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2225/06548 , H01L2225/06568 , H01L2225/06589 , H01L2924/00014 , H01L2924/01029 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2224/05552 , H01L2224/03
摘要： A method of multi-chip wafer level packaging comprises forming a reconfigured wafer using a plurality of photo-sensitive material layers. A plurality of semiconductor chips and wafers are embedded in the photo-sensitive material layers. Furthermore, a variety of through assembly vias are formed in the photo-sensitive material layers. Each semiconductor chip embedded in the photo-sensitive material layers is connected to input/output pads through connection paths formed by the through assembly vias.
摘要翻译：多芯片晶片级封装的方法包括使用多个感光材料层形成重新配置的晶片。多个半导体芯片和晶片被嵌入到感光材料层中。此外，在感光材料层中形成各种贯穿组装通孔。嵌入在感光材料层中的每个半导体芯片通过由通孔组装通孔形成的连接路径连接到输入/输出焊盘。

7. 发明申请

US20120061059A1 COOLING MECHANISM FOR STACKED DIE PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：堆叠式包装的冷却机构及其制造方法
公开(公告)号：US20120061059A1
公开(公告)日：2012-03-15
申请号：US13033840
申请日：2011-02-24
申请人： Yi-Li HSIAO , Chen-Hua Yu , Da-Yuan Shih , Chih-Hang Tung , Chun Hui Yu
发明人： Yi-Li HSIAO , Chen-Hua Yu , Da-Yuan Shih , Chih-Hang Tung , Chun Hui Yu
IPC分类号： F28D15/00
CPC分类号： F28D15/02 , H01L23/34 , H01L23/473 , H01L25/0657 , H01L25/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06589 , H01L2924/00014 , H01L2924/1461 , H01L2924/15788 , H01L2924/00 , H01L2224/0401
摘要： An apparatus for cooling a stacked die package comprises a first die provided above a substrate; a second die above the first die; a cooling fluid in fluid communication with the first die and the second die, the cooling fluid for absorbing thermal energy from the first and the second die; a housing containing the first and second dies, the housing sealing the first and second dies from an environment, wherein the housing further includes a first opening and a second opening, the first and second openings being vertically displaced from one another; a conduit having one end connected to the first opening and the other end connected to the second opening, the conduit allowing the cooling liquid to circulate from the first opening to the second opening; a first temperature sensor being arranged to provide an output that is dependent on a local temperature at the first opening; and a second temperature sensor being arranged to provide an output that is dependent on a local temperature at the second opening, wherein the outputs of the first and second temperature sensors relative to each other are indicative of a level of the cooling fluid.
摘要翻译：一种用于冷却堆叠的管芯封装的设备，包括设置在衬底上的第一管芯; 第一个模具上方的第二个模具; 与第一模具和第二模具流体连通的冷却流体，用于从第一模具和第二模具吸收热能的冷却流体; 壳体，其包含第一和第二模具，所述壳体将环境中的第一和第二模具密封，其中所述壳体还包括第一开口和第二开口，所述第一和第二开口彼此垂直移位; 导管，其一端连接到第一开口，另一端连接到第二开口，导管允许冷却液从第一开口循环到第二开口; 第一温度传感器被布置成提供依赖于第一开口处的局部温度的输出; 并且第二温度传感器被布置成提供取决于第二开口处的局部温度的输出，其中第一和第二温度传感器相对于彼此的输出指示冷却流体的水平。

8. 发明申请

US20130037950A1 Multi-Chip Wafer Level Package 有权
标题翻译：多芯片晶圆级封装
公开(公告)号：US20130037950A1
公开(公告)日：2013-02-14
申请号：US13206694
申请日：2011-08-10
申请人： Chun Hui Yu , Chih-Hang Tung , Tung-Liang Shao , Chen-Hua Yu , Da-Yuan Shih
发明人： Chun Hui Yu , Chih-Hang Tung , Tung-Liang Shao , Chen-Hua Yu , Da-Yuan Shih
IPC分类号： H01L23/485 , H01L21/82 , H01L21/56
CPC分类号： H01L23/481 , H01L21/563 , H01L21/568 , H01L21/76805 , H01L21/76838 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/5226 , H01L23/5389 , H01L24/16 , H01L24/19 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/19 , H01L2224/32145 , H01L2224/32245 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/8203 , H01L2224/94 , H01L2225/06513 , H01L2225/06524 , H01L2225/06548 , H01L2225/06568 , H01L2924/01029 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/18162 , H01L2924/351 , H01L2924/00 , H01L2224/03 , H01L2224/83005
摘要： A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.
摘要翻译：多芯片晶片级封装包括三个堆叠的半导体管芯。第一半导体管芯被嵌入在第一光敏材料层中。第二半导体管芯堆叠在第一半导体管芯的顶部上，其中第二半导体管芯与第一半导体管芯面对面连接。第三半导体管芯背靠背连接到第二半导体管芯。第二半导体管芯和第三半导体管芯都嵌入第二光敏材料层。多芯片晶片级封装还包括形成在第一光敏材料层和第二光敏材料层中的多个通过组装通孔。

9. 发明申请

US20130277829A1 Method of Fabricating Three Dimensional Integrated Circuit 有权
标题翻译：制造三维集成电路的方法
公开(公告)号：US20130277829A1
公开(公告)日：2013-10-24
申请号：US13452636
申请日：2012-04-20
申请人： Kuo-Chung Yee , Chun Hui Yu
发明人： Kuo-Chung Yee , Chun Hui Yu
IPC分类号： H01L23/498 , H01L21/56
CPC分类号： H01L23/49811 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/568 , H01L23/3128 , H01L23/498 , H01L23/49827 , H01L23/49894 , H01L24/10 , H01L24/81 , H01L24/97 , H01L2224/10 , H01L2224/16 , H01L2224/16225 , H01L2224/81 , H01L2224/81005 , H01L2224/97 , H01L2924/15311 , H01L2924/157 , H01L2924/15788 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component.
摘要翻译：一种制造三维集成电路的方法包括在包装部件的第一侧上形成再分配层，在再分布层中形成保持室，将集成电路管芯附接在包装部件的第一侧上，其中互连凸块的集成电路管芯插入到保持室中，对集成电路管芯和封装部件进行回流处理，并在封装部件上形成封装层。

10. 发明申请

US20140070348A1 Methods and Apparatus for Sensor Module 有权
标题翻译：传感器模块的方法和装置
公开(公告)号：US20140070348A1
公开(公告)日：2014-03-13
申请号：US13606289
申请日：2012-09-07
申请人： Kuo-Chung Yee , Chun Hui Yu
发明人： Kuo-Chung Yee , Chun Hui Yu
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H01L27/14632 , H01L23/481 , H01L27/14618 , H01L27/14621 , H01L27/14636 , H01L27/1464 , H01L27/14641 , H01L27/14683 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus for integrating a CMOS image sensor and an image signal processor (ISP) together using an interposer to form a system in package device module are disclosed. The device module may comprise an interposer with a substrate. An interposer contact is formed within the substrate. A sensor device may be bonded to a surface of the interposer, wherein a sensor contact is bonded to a first end of the interposer contact. An ISP may be connected to the interposer, by bonding an ISP contact in the ISP to a second end of the interposer contact. An underfill layer may fill a gap between the interposer and the ISP. A printed circuit board (PCB) may further be connected to the interposer by way of a solder ball connected to another interposer contact. A thermal interface material may be in contact with the ISP and the PCB.
摘要翻译：公开了使用插入器将CMOS图像传感器和图像信号处理器（ISP）集成在一起以形成封装器件模块中的系统的方法和装置。器件模块可以包括具有衬底的插入器。在衬底内形成插入物接触。传感器装置可以结合到插入件的表面，其中传感器触点被结合到插入件触点的第一端。 ISP可以通过将ISP中的ISP联系人连接到插入器联系人的第二端来连接到插入器。底层填充层可以填补插入件和ISP之间的间隙。印刷电路板（PCB）还可以通过连接到另一插入器触点的焊球连接到插入器。热界面材料可能与ISP和PCB接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式