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1. 发明授权

US07728384B2 Magnetic random access memory using single crystal self-aligned diode 有权
标题翻译：使用单晶自对准二极管的磁性随机存取存储器
公开(公告)号：US07728384B2
公开(公告)日：2010-06-01
申请号：US11420930
申请日：2006-05-30
申请人： Chiahua Ho , Yenhao Shih , Hsiang-Lan Lung
发明人： Chiahua Ho , Yenhao Shih , Hsiang-Lan Lung
IPC分类号： H01L23/62
CPC分类号： G11C11/16 , H01L27/224 , H01L43/08 , H01L43/12
摘要： A magnetic random access memory (MRAM) cell comprises a MRAM device and a single crystal self-aligned diode. The MRAM device and the single crystal self-aligned diode are connected through a contact. Only one metal line is positioned above the MRAM device of the MRAM cell. A first and second spacers positioned adjacent to the opposite sidewalls of the contact define the size of the single crystal self-aligned diode. A first and second metal silicide lines are positioned adjacent to the first and second spacers, respectively. The single crystal self-aligned diode, defined in a silicon substrate, includes a bottom implant (BI) region and a contact implant (CI) region. The CI region is surrounded by the BI region except for a side of the CI region that aligns the surface of the silicon substrate. A fabrication method, a read method, two programming methods for the MRAM cell are also disclosed.
摘要翻译：磁性随机存取存储器（MRAM）单元包括MRAM器件和单晶自对准二极管。 MRAM器件和单晶自对准二极管通过触点连接。在MRAM单元的MRAM器件上方只有一条金属线。靠近触点的相对侧壁定位的第一和第二间隔限定了单晶自对准二极管的尺寸。第一和第二金属硅化物线分别定位成与第一和第二间隔物相邻。限定在硅衬底中的单晶自对准二极管包括底部植入（BI）区域和接触植入（CI）区域。除了将硅衬底的表面对准的CI区域的一侧之外，CI区域被BI区域围绕。还公开了一种用于MRAM单元的制造方法，读取方法，两种编程方法。

2. 发明申请

US20070279978A1 MAGNETIC RANDOM ACCESS MEMORY USING SINGLE CRYSTAL SELF-ALIGNED DIODE 有权
标题翻译：使用单晶自对准二极管的磁性随机存取存储器
公开(公告)号：US20070279978A1
公开(公告)日：2007-12-06
申请号：US11420930
申请日：2006-05-30
申请人： Chiahua Ho , Yenhao Shih , Hsiang-Lan Lung
发明人： Chiahua Ho , Yenhao Shih , Hsiang-Lan Lung
IPC分类号： G11C11/14
CPC分类号： G11C11/16 , H01L27/224 , H01L43/08 , H01L43/12
摘要： A magnetic random access memory (MRAM) cell comprises a MRAM device and a single crystal self-aligned diode. The MRAM device and the single crystal self-aligned diode are connected through a contact. Only one metal line is positioned above the MRAM device of the MRAM cell. A first and second spacers positioned adjacent to the opposite sidewalls of the contact define the size of the single crystal self-aligned diode. A first and second metal silicide lines are positioned adjacent to the first and second spacers, respectively. The single crystal self-aligned diode, defined in a silicon substrate, includes a bottom implant (BI) region and a contact implant (CI) region. The CI region is surrounded by the BI region except for a side of the CI region that aligns the surface of the silicon substrate. A fabrication method, a read method, two programming methods for the MRAM cell are also disclosed.
摘要翻译：磁性随机存取存储器（MRAM）单元包括MRAM器件和单晶自对准二极管。 MRAM器件和单晶自对准二极管通过触点连接。在MRAM单元的MRAM器件上方只有一条金属线。靠近触点的相对侧壁定位的第一和第二间隔限定了单晶自对准二极管的尺寸。第一和第二金属硅化物线分别定位成与第一和第二间隔物相邻。限定在硅衬底中的单晶自对准二极管包括底部植入（BI）区域和接触植入（CI）区域。除了将硅衬底的表面对准的CI区域的一侧之外，CI区域被BI区域围绕。还公开了一种用于MRAM单元的制造方法，读取方法，两种编程方法。

3. 发明授权

US07514367B2 Method for manufacturing a narrow structure on an integrated circuit 有权
标题翻译：在集成电路上制造窄结构的方法
公开(公告)号：US07514367B2
公开(公告)日：2009-04-07
申请号：US11382739
申请日：2006-05-11
申请人： Hsiang Lan Lung , Chiahua Ho , Shih Hung Chen , Chieh Fang Chen
发明人： Hsiang Lan Lung , Chiahua Ho , Shih Hung Chen , Chieh Fang Chen
IPC分类号： H01L21/302
CPC分类号： H01L45/1226 , G11C13/0004 , H01L45/04 , H01L45/06 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1691 , Y10S438/947
摘要： A method of manufacturing for providing a narrow line, such as a phase change bridge, on a substrate having a top surface, includes first forming a layer of first material on the substrate. Then, a layer of a pattern material is applied on the layer of first material, and a pattern is defined. The pattern includes a ledge having a sidewall extending substantially to the layer of first material. A sidewall etch mask is formed on the ledge, and used to define a line of the first material on the substrate having a width substantially determined by the width of the sidewall etch mask.
摘要翻译：一种用于在具有顶表面的基底上提供诸如相变桥的窄线的制造方法包括首先在基底上形成第一材料层。然后，将图案材料层施加在第一材料层上，并且限定图案。该图案包括具有基本上延伸到第一材料层的侧壁的凸缘。侧壁蚀刻掩模形成在凸缘上，并且用于限定基板上的第一材料的线，其宽度基本上由侧壁蚀刻掩模的宽度决定。

4. 发明申请

US20060286743A1 Method for Manufacturing a Narrow Structure on an Integrated Circuit 有权
标题翻译：在集成电路上制造窄结构的方法
公开(公告)号：US20060286743A1
公开(公告)日：2006-12-21
申请号：US11382739
申请日：2006-05-11
申请人： Hsiang Lan Lung , Chiahua Ho , Shih Hung Chen , Chieh Chen
发明人： Hsiang Lan Lung , Chiahua Ho , Shih Hung Chen , Chieh Chen
IPC分类号： H01L21/8244 , H01L21/20
CPC分类号： H01L45/1226 , G11C13/0004 , H01L45/04 , H01L45/06 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1691 , Y10S438/947
摘要： A method of manufacturing for providing a narrow line, such as a phase change bridge, on a substrate having a top surface, includes first forming a layer of first material on the substrate. Then, a layer of a pattern material is applied on the layer of first material, and a pattern is defined. The pattern includes a ledge having a sidewall extending substantially to the layer of first material. A sidewall etch mask is formed on the ledge, and used to define a line of the first material on the substrate having a width substantially determined by the width of the sidewall etch mask.
摘要翻译：一种用于在具有顶表面的基底上提供诸如相变桥的窄线的制造方法包括首先在基底上形成第一材料层。然后，将图案材料层施加在第一材料层上，并且限定图案。该图案包括具有基本上延伸到第一材料层的侧壁的凸缘。侧壁蚀刻掩模形成在凸缘上，并且用于限定基板上的第一材料的线，其宽度基本上由侧壁蚀刻掩模的宽度决定。

5. 发明申请

US20090075466A1 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20090075466A1
公开(公告)日：2009-03-19
申请号：US12216679
申请日：2008-07-09
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/3205
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅极上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

6. 发明申请

US20070258284A1 METHODS AND APPARATUS FOR THERMALLY ASSISTED PROGRAMMING OF A MAGNETIC MEMORY DEVICE 有权
标题翻译：用于磁性记忆装置的热辅助编程的方法和装置
公开(公告)号：US20070258284A1
公开(公告)日：2007-11-08
申请号：US11381939
申请日：2006-05-05
申请人： Chiahua Ho , Kuang-Yeu Hsieh
发明人： Chiahua Ho , Kuang-Yeu Hsieh
IPC分类号： G11C11/14
CPC分类号： G11C11/16 , G11C11/1675
摘要： A magnetic memory device comprises a magnetic memory cell that includes a pinned layer and a free layer separated from the pinned layer by an insulating layer. The magnetic memory device also comprises a thermal plate in contact with the free layer. The magnetic memory device can be configured so that a first current flows through the thermal plate heating the thermal plate. The magnetic behavior of the free layer can be altered due to the heating caused by the first current, making it easier to switch the orientation and magnetization of the free layer. A second current can then flow through a bit line near the free layer generating a magnetic field sufficient to switch the orientation of magnetization of the free layer.
摘要翻译：磁存储器件包括磁存储单元，其包括被钉扎层和通过绝缘层与被钉扎层分离的自由层。磁存储装置还包括与自由层接触的热板。磁存储器件可以被配置成使得第一电流流过加热板的加热板。由于由第一电流引起的加热，自由层的磁性能可以改变，从而更容易切换自由层的取向和磁化。然后，第二电流可以流过自由层附近的位线，产生足以切换自由层的磁化取向的磁场。

7. 发明申请

US20050105328A1 Perpendicular MRAM with high magnetic transition and low programming current 审中-公开
标题翻译：具有高磁转移和低编程电流的垂直MRAM
公开(公告)号：US20050105328A1
公开(公告)日：2005-05-19
申请号：US10715670
申请日：2003-11-17
申请人： Chiahua Ho
发明人： Chiahua Ho
IPC分类号： G11C11/00 , G11C11/15 , G11C11/16
CPC分类号： G11C11/16
摘要： An invention is provided for a magnetic random access memory (MRAM) cell. The MRAM cell includes a first wordline and a first bitline perpendicular to the wordline. Disposed at an intersection of the first wordline and the first bitline is an MTJ device having a perpendicular magnetic orientation. To program the MRAM cell, current is driven through the two bitlines and two wordlines that are adjacent to the memory cell. As a result, the MRAM cell has a high magnetic transition and low programming current.
摘要翻译：本发明提供一种磁性随机存取存储器（MRAM）单元。 MRAM单元包括第一字线和垂直于字线的第一位线。在第一字线和第一位线的交点处设置有具有垂直磁方位的MTJ装置。为了编程MRAM单元，电流通过与存储单元相邻的两个位线和两个字线驱动。结果，MRAM单元具有高磁转移和低编程电流。

8. 发明授权

US07605079B2 Manufacturing method for phase change RAM with electrode layer process 有权
标题翻译：具有电极层工艺的相变RAM的制造方法
公开(公告)号：US07605079B2
公开(公告)日：2009-10-20
申请号：US11382799
申请日：2006-05-11
申请人： Erh Kun Lai , Chiahua Ho , Yi Chou Chen , Kuang Yeu Hsieh
发明人： Erh Kun Lai , Chiahua Ho , Yi Chou Chen , Kuang Yeu Hsieh
IPC分类号： H01L21/44
CPC分类号： H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A method for manufacturing a phase change memory device comprises forming an electrode layer. Electrodes are made in the electrode layer using conductor fill techniques that are also used inter-layer conductors for metallization layers, in order to improve process scaling with shrinking critical dimensions for metallization layers. The electrode layer is made by forming a multi-layer dielectric layer on a substrate, etching the multi-layer dielectric layer to form vias for electrode members contacting circuitry below, forming insulating spacers on the vias, etching through a top layer in the multi-layer dielectric layer to form trenches between the insulating spacers for electrode members contacting circuitry above, filling the vias and trenches with a conductive material using the metallization process. Thin film bridges of memory material are formed over the electrode layer.
摘要翻译：一种相变存储器件的制造方法，包括形成电极层。使用导体填充技术在电极层中制造电极，该技术也用于金属化层的层间导体，以便通过金属化层的缩小临界尺寸改善工艺规模。电极层是通过在衬底上形成多层电介质层而形成的，蚀刻多层电介质层以形成接触下面电路的电极构件的通路，在通孔上形成绝缘隔离层，以在用于接触上述电路的电极部件的绝缘间隔物之间形成沟槽，用导电材料使用金属化工艺填充过孔和沟槽。存储材料的薄膜桥形成在电极层上。

9. 发明授权

US07599217B2 Memory cell device and manufacturing method 有权
标题翻译：存储单元器件及其制造方法
公开(公告)号：US07599217B2
公开(公告)日：2009-10-06
申请号：US11357902
申请日：2006-02-17
申请人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
IPC分类号： G11C11/00
CPC分类号： H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1691
摘要： A memory cell device, having a memory material switchable between electrical property states by the application of energy, comprises an electrode, a separation layer against an electrode surface, a hole in the separation layer, a second material in the hole defining a void having a downwardly and inwardly tapering void region. A memory material is in the void region in electrical contact with the electrode surface. A second electrode is in electrical contact with the memory material. Energy passing between the first and second electrodes is concentrated within the memory material so to facilitate changing an electrical property state of the memory material. The memory material may comprise a phase change material. The second material may comprise a high density plasma-deposited material. A method for making a memory cell device is also discussed.
摘要翻译：具有可通过施加能量在电性能状态之间切换的记忆材料的存储单元装置包括电极，与电极表面相对的分离层，分离层中的孔，孔中的第二材料限定具有向下和向内逐渐变细的空隙区域。记忆材料位于与电极表面电接触的空隙区域中。第二电极与记忆材料电接触。在第一和第二电极之间的能量通过集中在存储材料内，以便于改变存储材料的电性能状态。记忆材料可以包括相变材料。第二材料可以包括高密度等离子体沉积材料。还讨论了制造存储单元器件的方法。

10. 发明申请

US20090239358A1 Memory Device Manufacturing Method 有权
标题翻译：存储器件制造方法
公开(公告)号：US20090239358A1
公开(公告)日：2009-09-24
申请号：US12469184
申请日：2009-05-20
申请人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
IPC分类号： H01L21/28
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1253 , H01L45/14 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A method for making a memory device includes providing a dielectric material, having first and second upwardly and inwardly tapering surfaces and a surface segment connecting the first and second surfaces. First and second electrodes are formed over the first and second surfaces. A memory element is formed over the surface segment to electrically connect the first and second electrodes.
摘要翻译：制造存储器件的方法包括提供具有第一和第二向上和向内渐缩的表面的电介质材料以及连接第一和第二表面的表面段。第一和第二电极形成在第一和第二表面上。存储元件形成在表面段上以电连接第一和第二电极。

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