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1. 发明授权

US11544072B2 Memory-network processor with programmable optimizations 有权
公开(公告)号：US11544072B2
公开(公告)日：2023-01-03
申请号：US17203205
申请日：2021-03-16
申请人： Coherent Logix, Incorporated
发明人： Michael B. Doerr , Carl S. Dobbs , Michael B. Solka , Michael R. Trocino , Kenneth R. Faulkner , Keith M. Bindloss , Sumeer Arya , John Mark Beardslee , David A. Gibson
IPC分类号： G06F9/38 , G06F9/30 , G06F12/02
摘要： Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. First and second address generator units may generate, based on different fields of the multi-part instruction, addresses from which to retrieve first and second data for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction. The execution units may perform operations using a single pipeline or multiple pipelines based on third and fourth fields of the multi-part instruction.

2. 发明申请

US20210034566A1 Memory Network Processor 有权
公开(公告)号：US20210034566A1
公开(公告)日：2021-02-04
申请号：US16931864
申请日：2020-07-17
申请人： Coherent Logix, Incorporated
发明人： Carl S. Dobbs , Keith M. Bindloss , Kenneth R. Faulkner , Alex E. Icaza , Frederick A. Rush , Faisal A. Syed , Michael R. Trocino
IPC分类号： G06F15/173 , G06F9/54 , H04L12/741
摘要： A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.

3. 发明申请

US20190155761A1 Multiprocessor System with Improved Secondary Interconnection Network 审中-公开
公开(公告)号：US20190155761A1
公开(公告)日：2019-05-23
申请号：US16252827
申请日：2019-01-21
申请人： Coherent Logix, Incorporated
发明人： Carl S. Dobbs , Michael R. Trocino
IPC分类号： G06F13/16 , G06F13/40 , G06F15/78 , G06F13/42 , G06F13/362 , G06F9/4401 , G06F15/173
摘要： Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

4. 发明申请

US20170286196A1 Processing System With Interspersed Processors With Multi-Layer Interconnection 有权
公开(公告)号：US20170286196A1
公开(公告)日：2017-10-05
申请号：US15631925
申请日：2017-06-23
申请人： Coherent Logix, Incorporated
发明人： Carl S. Dobbs , Michael R. Trocino , Michael B. Solka
IPC分类号： G06F9/54 , G06F13/40 , G06F13/42 , G06F15/80
CPC分类号： G06F9/546 , G06F9/44505 , G06F13/1673 , G06F13/28 , G06F13/4022 , G06F13/4027 , G06F13/4282 , G06F15/76 , G06F15/8038 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.

5. 发明申请

US20160370823A1 CLOCK DISTRIBUTION NETWORK FOR MULTI-FREQUENCY MULTI-PROCESSOR SYSTEMS 有权
标题翻译：用于多频多处理器系统的时钟分配网络
公开(公告)号：US20160370823A1
公开(公告)日：2016-12-22
申请号：US15253372
申请日：2016-08-31
申请人： COHERENT LOGIX, INCORPORATED
发明人： Carl S. Dobbs , Michael R. Trocino , Kenneth R. Faulkner , Christopher L. Schreppel
IPC分类号： G06F1/12 , H03L7/08 , G06F21/75 , G06F1/32 , G06F1/10 , H03K3/03 , G06F1/08
CPC分类号： G06F1/12 , G06F1/04 , G06F1/08 , G06F1/10 , G06F1/324 , G06F11/1604 , G06F21/75 , H03K3/0315 , H03L7/06 , H03L7/08 , H03L7/085 , Y02D10/126
摘要： Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. A clock signal generated on-chip with the synchronous digital system may be automatically selected in response to detecting a condition indicating that use of a local clock may be necessary. Such conditions may include detection of tampering with the synchronous digital system. If an indication of tampering is detected, security measures may be performed.
摘要翻译：公开了可以包括时钟和同步信号的产生的同步数字系统的实施例。可以选择多个可用时钟信号中的任何一个用作主时钟，而不会在同步数字系统中引起时钟引起的错误。响应于检测到指示可能需要使用本地时钟的条件，可以自动选择与同步数字系统一起在片上产生的时钟信号。这种情况可能包括检测同步数字系统的篡改。如果检测到篡改的指示，则可以执行安全措施。

6. 发明申请

US20160328231A1 MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS 审中-公开
标题翻译：具有可编程优化的存储网络处理器
公开(公告)号：US20160328231A1
公开(公告)日：2016-11-10
申请号：US15211134
申请日：2016-07-15
申请人： COHERENT LOGIX, INCORPORATED
发明人： Michael B. Doerr , Carl S. Dobbs , Michael B. Solka , Michael R. Trocino , Kenneth R. Faulkner , Keith M. Bindloss , Sumeer Arya , John Mark Beardslee , David A. Gibson
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3005 , G06F9/30083 , G06F9/30145 , G06F9/30181 , G06F9/3802 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F12/0215
摘要： In some embodiments, an apparatus includes processing circuitry that includes a plurality of different components configured to perform operations to generate execution results for instructions executed by the apparatus. In some embodiments the apparatus includes front-end circuitry configured to retrieve a plurality of instructions for execution and, based on identification of one or more instruction characteristics of the plurality of instructions, selectively disable one or more portions of the processing circuitry for one or more cycles during execution of the plurality of instructions. In some embodiments, this may reduce power consumption by the apparatus.
摘要翻译：在一些实施例中，一种装置包括处理电路，该处理电路包括被配置为执行操作以生成由该装置执行的指令的执行结果的多个不同部件。在一些实施例中，该装置包括被配置为检索用于执行的多个指令的前端电路，并且基于多个指令的一个或多个指令特性的识别，选择性地禁止一个或多个处理电路的一个或多个部分在执行多个指令期间循环。在一些实施例中，这可以减少设备的功耗。

7. 发明授权

US09450590B2 Clock distribution network for multi-frequency multi-processor systems 有权
标题翻译：多频多处理器系统的时钟分配网络
公开(公告)号：US09450590B2
公开(公告)日：2016-09-20
申请号：US14106138
申请日：2013-12-13
申请人： COHERENT LOGIX, INCORPORATED
发明人： Carl S. Dobbs , Michael R. Trocino , Kenneth R. Faulkner , Christopher L. Schreppel
IPC分类号： G06F1/04 , G08B29/00 , H03L7/085 , H03L7/08 , G06F1/12 , G06F1/08 , G06F11/16 , G06F21/75 , H03L7/06 , G06F1/10
CPC分类号： G06F1/12 , G06F1/04 , G06F1/08 , G06F1/10 , G06F1/324 , G06F11/1604 , G06F21/75 , H03K3/0315 , H03L7/06 , H03L7/08 , H03L7/085 , Y02D10/126
摘要： Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. The clock signals may be selected automatically or programmatically. Clock generation circuitry may generate a clock signal that is initially used as the primary clock. The clock generation circuitry may be dynamically reconfigured without interrupting operation of the synchronous digital system, by first selecting another of the available clock signals for use as the primary clock.
摘要翻译：公开了可以包括时钟和同步信号的产生的同步数字系统的实施例。可以选择多个可用时钟信号中的任何一个用作主时钟，而不会在同步数字系统中引起时钟引起的错误。可以自动或以编程方式选择时钟信号。时钟产生电路可以产生最初用作主时钟的时钟信号。可以通过首先选择可用的时钟信号中的另一个用作主时钟，来动态地重新配置时钟产生电路而不中断同步数字系统的操作。

8. 发明申请

US20160196234A1 PROCESSING SYSTEM WITH SYNCHRONIZATION INSTRUCTION 有权
标题翻译：具有同步指令的处理系统
公开(公告)号：US20160196234A1
公开(公告)日：2016-07-07
申请号：US15073276
申请日：2016-03-17
申请人： COHERENT LOGIX, INCORPORATED
发明人： Carl S. Dobbs , Afzal M. Malik , Kenneth R. Faulkner , Michael B. Solka
IPC分类号： G06F15/76
CPC分类号： G06F15/76 , G06F9/522
摘要： Embodiments of a multi-processor array are disclosed that may include a plurality of processors, and controllers. Each processor may include a plurality of processor ports and a sync adapter. Each sync adapter may include a plurality of adapter ports. Each controller may include a plurality of controller ports, and a configuration port. The plurality of processors and the plurality of controllers may be coupled together in an interspersed arrangement, and the controllers may be distinct from the processors. Each processor may be configured to send a synchronization signal through its adapter ports to one or more controllers, and to pause execution of program instructions while waiting for a response from the one or more controllers.
摘要翻译：公开了可以包括多个处理器和控制器的多处理器阵列的实施例。每个处理器可以包括多个处理器端口和同步适配器。每个同步适配器可以包括多个适配器端口。每个控制器可以包括多个控制器端口和配置端口。多个处理器和多个控制器可以以散置的布置耦合在一起，并且控制器可以与处理器不同。每个处理器可以被配置为通过其适配器端口向一个或多个控制器发送同步信号，并且在等待来自一个或多个控制器的响应的同时暂停程序指令的执行。

9. 发明授权

US09292464B2 Multiprocessor system with improved secondary interconnection network 有权
标题翻译：具有改进的二次互连网络的多处理器系统
公开(公告)号：US09292464B2
公开(公告)日：2016-03-22
申请号：US14086648
申请日：2013-11-21
申请人： COHERENT LOGIX, INCORPORATED
发明人： Carl S. Dobbs , Michael R. Trocino
IPC分类号： G06F13/36 , H04L12/56 , G06F13/40 , G06F15/173 , G06F15/78
CPC分类号： G06F13/1652 , G06F9/4401 , G06F13/362 , G06F13/4022 , G06F13/4027 , G06F13/4068 , G06F13/4282 , G06F15/17381 , G06F15/7817 , G06F15/7882 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.
摘要翻译：公开了一种多处理器系统的实施例，其可以包括散布有多个数据存储器路由器，多个总线接口单元，总线控制电路和处理器接口电路的多个处理器。数据存储器路由器可以耦合在一起以形成主互连网络。总线接口单元和总线控制电路可以以菊花链方式耦合在一起以形成辅助互连网络。每个总线接口单元可以被配置为将数据或指令读取或写入到多个数据存储器路由器中的相应一个数据存储器路由器和相应的处理器。与处理器接口电路耦合的总线控制电路可以被配置为用作主要和次要网络之间的双向桥接器。总线控制电路还可以耦合到其他接口电路并仲裁他们对辅助网络的访问。

10. 发明申请

US20140143470A1 Processing System With Interspersed Processors DMA-FIFO 有权
标题翻译：处理系统与散布处理器DMA-FIFO
公开(公告)号：US20140143470A1
公开(公告)日：2014-05-22
申请号：US13791345
申请日：2013-03-08
申请人： COHERENT LOGIX, INCORPORATED
发明人： Carl S. Dobbs , Michael R. Trocino , Keith M. Bindloss
IPC分类号： G06F13/28
CPC分类号： G06F9/546 , G06F9/44505 , G06F13/1673 , G06F13/28 , G06F13/4022 , G06F13/4027 , G06F13/4282 , G06F15/76 , G06F15/8038 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.
摘要翻译：公开了可以包括多个处理器，本地存储器，可配置通信元件和直接存储器访问（DMA）引擎以及DMA控制器的多处理器阵列的实施例。每个处理器可以耦合到本地存储器之一，并且多个处理器，本地存储器和可配置通信元件可以以散置的布置耦合在一起。 DMA控制器可以被配置为控制多个DMA引擎的操作。

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