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1. 发明授权

US08791754B2 Programmable gain amplifier with amplifier common mode sampling system 有权
标题翻译：具有放大器共模采样系统的可编程增益放大器
公开(公告)号：US08791754B2
公开(公告)日：2014-07-29
申请号：US13592074
申请日：2012-08-22
申请人： Colin G. Lyden , Roberto S. Maurino , Damien J. McCartney
发明人： Colin G. Lyden , Roberto S. Maurino , Damien J. McCartney
IPC分类号： H03F1/02
CPC分类号： H03G3/008
摘要： A programmable gain amplifier (“PGA”) may include a differential amplifier, a pair of input capacitors, a pair of feedback capacitors provided in feedback configuration about the amplifier, a first chop circuit, provided at an input of the PGA and an output of the PGA and a second chop circuit provided at an output of the PGA. The PGA also may include circuit systems to sample voltages across the input capacitors in a sampling phase. The sampled voltages may correspond to a difference between a common mode voltage of input signals to the PGA and a common mode voltage of the differential amplifier. The sampled voltage, thus, defines a common mode voltage at the amplifier's inputs during other phases of operation, when the chop circuits are operational.
摘要翻译：可编程增益放大器（“PGA”）可以包括差分放大器，一对输入电容器，在放大器的反馈配置中提供的一对反馈电容器，设置在PGA输入端的第一斩波电路， PGA和设置在PGA输出端的第二斩波电路。 PGA还可以包括在采样阶段对输入电容器两端的电压进行采样的电路系统。采样电压可以对应于PGA的输入信号的共模电压与差分放大器的共模电压之间的差。因此，当斩波电路工作时，采样电压在其他操作阶段确定放大器输入端的共模电压。

2. 发明授权

US08766836B2 Sigma delta modulator with dither 有权
标题翻译：具有抖动的Sigma delta调制器
公开(公告)号：US08766836B2
公开(公告)日：2014-07-01
申请号：US13715005
申请日：2012-12-14
申请人： Roberto S. Maurino , Colin G. Lyden
发明人： Roberto S. Maurino , Colin G. Lyden
IPC分类号： H03M3/00
CPC分类号： H03M3/30 , H03M3/328 , H03M3/422
摘要： A sigma delta modulator may include a loop filter and an adder configured to accept an output of the loop filter and a dither input signal. The adder may be further configured to combine the output of the loop filter and the dither input signal into a combined output signal. The sigma delta modulator may further include a quantizer configured to accept the combined output signal from the adder, and quantize the combined signal into a quantizer output signal. The sigma delta modulator may further include a first subtractor configured to accept the quantizer output signal and subtract the dither input signal from the quantizer output signal.
摘要翻译： Σ-Δ调制器可以包括环路滤波器和被配置为接受环路滤波器的输出和抖动输入信号的加法器。加法器可以被进一步配置为将环路滤波器的输出和抖动输入信号组合成组合的输出信号。 Σ-Δ调制器还可以包括量化器，其被配置为接受来自加法器的组合输出信号，并将组合信号量化为量化器输出信号。 Σ-Δ调制器还可以包括：第一减法器，被配置为接受量化器输出信号，并从量化器输出信号中减去抖动输入信号。

3. 发明授权

US09124290B2 Method and apparatus for separating the reference current from the input signal in sigma-delta converter 有权
标题翻译：用于在Σ-Δ转换器中分离参考电流与输入信号的方法和装置
公开(公告)号：US09124290B2
公开(公告)日：2015-09-01
申请号：US13757455
申请日：2013-02-01
申请人： Adrian W. Sherry , Gabriel Banarie , Roberto S. Maurino
发明人： Adrian W. Sherry , Gabriel Banarie , Roberto S. Maurino
IPC分类号： H03M3/00 , G06G7/184
CPC分类号： H03M3/30 , G06G7/184 , H03M3/322 , H03M3/358 , H03M3/458 , H03M3/496
摘要： An integrator system may have a pair of sampling circuits each having a sampling capacitor to sample a respective component of a differential input signal, and an integrator having inputs coupled to outputs of the sampling circuits. The system may have a shorting switch coupled between input terminals of the sampling capacitors. The shorting switch may be engaged during an interstitial phase between sampling and output phases of the sampling circuits. By shorting input terminals of the sampling capacitors together, the design reduces current drawn by the system and, in some designs, severs relationships between current draw and information content sampled by the system. The integrator system may receive analog and digital input signals.
摘要翻译：积分器系统可以具有一对采样电路，每个采样电路各自具有采样电容器以对差分输入信号的相应分量进行采样，以及具有耦合到采样电路的输出的输入的积分器。该系统可以具有耦合在采样电容器的输入端之间的短路开关。在采样电路的采样和输出阶段之间的间隙阶段，短路开关可能被接合。通过将采样电容器的输入端子短路在一起，该设计减少了系统吸收的电流，并且在一些设计中，切断了电流抽取与系统采样的信息内容之间的关系。积分器系统可以接收模拟和数字输入信号。

4. 发明授权

US08779958B1 Continuous time input stage 有权
标题翻译：连续时间输入级
公开(公告)号：US08779958B1
公开(公告)日：2014-07-15
申请号：US13747241
申请日：2013-01-22
申请人： Roberto S. Maurino , Sanjay Rajasekhar , Abhilasha Kawle
发明人： Roberto S. Maurino , Sanjay Rajasekhar , Abhilasha Kawle
IPC分类号： H03M1/66 , H03M3/00 , H03M1/74
CPC分类号： H03M3/35 , H03M3/376 , H03M3/47
摘要： A continuous time input stage including a first digital-to-analog converter (DAC) including a first DAC code input, a second DAC including a second DAC code input, a first set of switches coupled to the output of the first DAC, a second set of switches coupled to the output of the second DAC, and an amplifier configured to receive the output of either the first DAC or the second DAC.
摘要翻译：连续时间输入级包括包括第一DAC代码输入的第一数模转换器（DAC），包括第二DAC代码输入的第二DAC，耦合到第一DAC的输出的第一组开关，第二DAC 耦合到第二DAC的输出的开关组以及被配置为接收第一DAC或第二DAC的输出的放大器。

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