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1. 发明授权

US09673329B2 Method for manufacturing a fin MOS transistor 有权
公开(公告)号：US09673329B2
公开(公告)日：2017-06-06
申请号：US14959430
申请日：2015-12-04
申请人： STMicroelectronics SA , Commissariat A L'Energie Atomique et aux Energies Alternatives
发明人： Yves Morand , Romain Wacquez , Laurent Grenouillet , Yannick Le Tiec , Maud Vinet
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78
CPC分类号： H01L29/785 , H01L27/1211 , H01L29/0649 , H01L29/0657 , H01L29/66795 , H01L29/66818 , H01L29/7856
摘要： A fin MOS transistor is made from an SOI-type structure that includes a semiconductor layer on a silicon oxide layer coating a semiconductor support. A trench formed from the surface of the semiconductor layer delimits at least one fin in the semiconductor layer, that trench extending at least to an upper surface of the semiconductor support. Etched recesses in sides of a portion of the silicon oxide layer located under the fin are filled with a material selectively etchable over silicon oxide.

2. 发明授权

US11264479B2 Process for producing FET transistors 有权
公开(公告)号：US11264479B2
公开(公告)日：2022-03-01
申请号：US14426007
申请日：2013-09-04
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Laurent Grenouillet , Maud Vinet , Romain Wacquez
IPC分类号： H01L29/66 , H01L29/786 , H01L29/423 , H01L29/10 , H01L21/265 , H01L21/28 , H01L21/3065 , H01L29/06 , H01L29/78
摘要： A method of production of a field-effect transistor from a stack of layers forming a semiconductor-on-insulator type substrate, the stack including a superficial layer of an initial thickness, made of a crystalline semiconductor material and covered with a protective layer, the method including: defining, by photolithography, a gate pattern in the protective layer; etching the gate pattern into the superficial layer to leave a thickness of the layer of semiconductor material in place, the thickness defining a height of a conduction channel of the field-effect transistor; forming a gate in the gate pattern; forming, in the superficial layer and on either side of the gate, source and drain zones, while preserving, in the zones, the initial thickness of the superficial layer.

3. 发明授权

US09991892B2 Electronic device having a physical unclonable function identifier 有权
公开(公告)号：US09991892B2
公开(公告)日：2018-06-05
申请号：US15600331
申请日：2017-05-19
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Romain Wacquez , Jacques Fournier , Carlo Reita
IPC分类号： H01L23/00 , H03K19/003 , H01L27/11 , G06F21/44
CPC分类号： H03K19/00315 , G06F21/44 , H01L23/544 , H01L23/576 , H01L27/1104 , H01L2223/54413 , H01L2223/5444 , H01L2223/54473
摘要： Electronic device comprising at least: a plurality of MOSFET FD-SOI type transistors among which the first transistors are such that each first transistor comprises a channel in which a concentration of the same type of dopants as those present in the source and drain of said first transistor is greater than the concentration in the channel of each of the other transistors in said plurality of transistors; and an identification circuit capable of determining a unique identifier of the electronic device starting from at least one intrinsic electrical characteristic of each of the first transistors, the value of which depends at least partly on the conductance of said first transistor; and in which the length of a gate of each of the first transistors is less than or equal to about 20 nm.

4. 发明授权

US09460971B2 Method to co-integrate oppositely strained semiconductor devices on a same substrate 有权
公开(公告)号：US09460971B2
公开(公告)日：2016-10-04
申请号：US14955801
申请日：2015-12-01
申请人： STMICROELECTRONICS, INC. , COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Nicolas Loubet , Sylvain Maitrejean , Romain Wacquez
IPC分类号： H01L21/84 , H01L27/12 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/78 , H01L29/06 , H01L21/762 , H01L21/265 , H01L21/324 , H01L21/266 , H01L21/306 , H01L21/02 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/845 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/26506 , H01L21/266 , H01L21/306 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/76283 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/0649 , H01L29/1054 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/7847 , H01L29/7848 , H01L29/7849
摘要： Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.

5. 发明授权

US09437475B2 Method for fabricating microelectronic devices with isolation trenches partially formed under active regions 有权
标题翻译：用于制造具有在有源区域部分形成的隔离沟槽的微电子器件的方法
公开(公告)号：US09437475B2
公开(公告)日：2016-09-06
申请号：US14441354
申请日：2012-11-08
申请人： Commissariat a l'energie atomique et aux energies alternatives
发明人： Maud Vinet , Sylvie Mignot , Romain Wacquez
IPC分类号： H01L21/762 , H01L21/84 , H01L21/311 , H01L29/06
CPC分类号： H01L21/76283 , H01L21/311 , H01L21/76232 , H01L21/84 , H01L29/0649
摘要： A method of producing a microelectronic device in a substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer, including: etching a trench through the first semiconductor layer, the first dielectric layer, and a part of the second semiconductor layer, defining one active region, and such that, at the level of the second semiconductor layer, a part of the trench extends under a part of the active region; deposition of one second dielectric layer in the trench; etching the second dielectric layer such that remaining portions of the second dielectric layer forms portions of dielectric material extending under a part of the active region; deposition of a third dielectric layer in the trench such that the trench is filled with the dielectric materials of the second and third dielectric layers and forms an isolation trench.
摘要翻译：一种在包括第一半导体层，第一介电层和第二半导体层的衬底中制造微电子器件的方法，包括：通过第一半导体层，第一电介质层和第二半导体的一部分蚀刻沟槽层，限定一个有源区，并且使得在第二半导体层的水平处，沟槽的一部分在有源区的一部分下延伸; 在沟槽中沉积一个第二介电层; 蚀刻第二电介质层，使得第二电介质层的剩余部分形成在有源区的一部分下延伸的电介质材料的部分; 在沟槽中沉积第三电介质层，使得沟槽被第二和第三电介质层的电介质材料填充并形成隔离沟槽。

6. 发明授权

US08954363B2 Digital-to-analogue converter and neuromorphic circuit using such a converter 有权
标题翻译：使用这种转换器的数模转换器和神经形态电路
公开(公告)号：US08954363B2
公开(公告)日：2015-02-10
申请号：US13705031
申请日：2012-12-04
申请人： Commissariat a l'Energie Atomique et aux Energies Alternatives
发明人： Rodolphe Heliot , Xavier Jehl , Marc Sanquer , Romain Wacquez
IPC分类号： G06N3/04 , H03M1/06 , H03M1/10 , G06N3/02 , H03M1/80 , G06N3/063 , H03M1/74
CPC分类号： G06N3/02 , G06N3/0635 , H03M1/0653 , H03M1/1042 , H03M1/747 , H03M1/80
摘要： A digital-to-analogue converter, with application to electronic circuits with neuromorphic architecture, comprises: transistors of identical nominal geometrical characteristics, but of dispersed current-voltage characteristics, wherein when a constant gate-source voltage is applied to the different transistors, a current varying as a function of the dispersion circulates in the transistor; a digital table receiving a digital word and having a selection output selecting, as a function of the word to be converted, a transistor or transistors supplying a current of desired value representing this word in analogue form. The look-up table is loaded as a function of real measured current-voltage characteristics of different transistors of the set, to establish a look-up between words and current values. The wide variability of characteristics of the transistors, notably their leakage current for a gate-source voltage below the switch-on threshold, allows finding combinations of leakage currents which are a good representation of words to be converted.
摘要翻译：应用于具有神经形态结构的电子电路的数模转换器包括：具有相同标称几何特性但具有分散的电流 - 电压特性的晶体管，其中当恒定的栅极 - 源极电压施加到不同的晶体管时，作为色散的函数的电流随晶体管循环而变化; 接收数字字并且具有选择输出的数字表作为要转换的字的函数，以模拟形式提供表示该字的期望值的电流的晶体管或晶体管。查找表作为集合中不同晶体管的实际测量电流 - 电压特性的函数加载，以建立词和当前值之间的查找。晶体管的特性的广泛变化，特别是其栅极 - 源极电压的低于开启阈值的泄漏电流，允许找到泄漏电流的组合，这是要转换的字的良好表示。

7. 发明申请

US20150294904A1 METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER ACTIVE REGIONS 有权
标题翻译：用于在有源区域部分地形成隔离斜面的微电子器件制造方法
公开(公告)号：US20150294904A1
公开(公告)日：2015-10-15
申请号：US14441354
申请日：2012-11-08
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Maud Vinet , Sylvie Mignot , Romain Wacquez
IPC分类号： H01L21/762 , H01L29/06 , H01L21/311
CPC分类号： H01L21/76283 , H01L21/311 , H01L21/76232 , H01L21/84 , H01L29/0649
摘要： A method of producing a microelectronic device in a substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer, including: etching a trench through the first semiconductor layer, the first dielectric layer, and a part of the second semiconductor layer, defining one active region, and such that, at the level of the second semiconductor layer, a part of the trench extends under a part of the active region; deposition of one second dielectric layer in the trench; etching the second dielectric layer such that remaining portions of the second dielectric layer forms portions of dielectric material extending under a part of the active region; deposition of a third dielectric layer in the trench such that the trench is filled with the dielectric materials of the second and third dielectric layers and forms an isolation trench.
摘要翻译：一种在包括第一半导体层，第一介电层和第二半导体层的衬底中制造微电子器件的方法，包括：通过第一半导体层，第一电介质层和第二半导体的一部分蚀刻沟槽层，限定一个有源区，并且使得在第二半导体层的水平处，沟槽的一部分在有源区的一部分下延伸; 在沟槽中沉积一个第二介电层; 蚀刻第二电介质层，使得第二电介质层的剩余部分形成在有源区的一部分下延伸的电介质材料的部分; 在沟槽中沉积第三电介质层，使得沟槽被第二和第三电介质层的电介质材料填充并形成隔离沟槽。

8. 发明授权

US08877618B2 Method for producing a field effect transistor with a SiGe channel by ion implantation 有权
标题翻译：通过离子注入制造具有SiGe通道的场效应晶体管的方法
公开(公告)号：US08877618B2
公开(公告)日：2014-11-04
申请号：US14073402
申请日：2013-11-06
申请人： Commissariat a l'Energie Atomique et aux Energies Alternatives
发明人： Laurent Grenouillet , Maud Vinet , Yannick Le Tiec , Romain Wacquez , Olivier Faynot
IPC分类号： H01L21/20 , H01L21/266 , H01L29/66 , H01L29/78 , H01L21/265 , H01L29/786 , H01L29/165
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/26586 , H01L21/266 , H01L29/165 , H01L29/66742 , H01L29/66772 , H01L29/7848 , H01L29/78684
摘要： The semiconductor-on-insulator substrate includes a support, an electrically insulating film, a crystalline film made from semiconductor material, and a protection layer. Germanium ions are implanted in the semiconductor material film through the protection layer so as to form an amorphized area in contact with the protection layer and a crystalline area in contact with the electrically insulating film. The semiconductor material film is annealed so as to recrystallize the amorphized area from the crystalline area.
摘要翻译：绝缘体上半导体衬底包括支撑体，电绝缘膜，由半导体材料制成的结晶膜和保护层。通过保护层将锗离子注入到半导体材料膜中，以形成与保护层接触的非晶形区域和与电绝缘膜接触的结晶区域。对半导体材料膜进行退火以使结晶区域的非晶化区域再结晶。

9. 发明授权

US10355207B2 Method for forming a non-volatile memory cell, non-volatile memory cell formed according to said method and microelectronic device comprising such memory cells 有权
公开(公告)号：US10355207B2
公开(公告)日：2019-07-16
申请号：US15927635
申请日：2018-03-21
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , UNIVERSITE D'AIX-MARSEILLE , CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)
发明人： Alexis Krakovinsky , Marc Bocquet , Jean Coignus , Vincenzo Della Marca , Jean-Michel Portal , Romain Wacquez
IPC分类号： G11C11/00 , H01L45/00 , G11C13/00 , H01L21/66 , H01L27/24 , G11C7/00 , G11C13/04
摘要： A method for forming a non-volatile memory cell intended to switch the memory cell from an unformed state to a formed state, the memory cell including an ordered stack of a lower electrode, a layer of insulating material and an upper electrode. The forming method includes a breakdown operation in which at least one laser shot is emitted towards the layer of insulating material to make the layer of insulating material active by making it pass from a high resistance state to a low resistance state, the memory cell being formed when the layer of insulating material is active.

10. 发明申请

US20190172526A1 SRAM MEMORY HAVING A FAST CLEAR 审中-公开
公开(公告)号：US20190172526A1
公开(公告)日：2019-06-06
申请号：US16210663
申请日：2018-12-05
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Jean-Philippe Noel , Noemie Boher , Romain Wacquez
IPC分类号： G11C11/419 , G11C11/417 , G11C11/418 , G11C11/412
摘要： Static random access memory device comprising a memory matrix provided with at least one column (COL1) formed from a plurality of SRAM memory cells (C11, CN1), the device being provided with a fast erase memory circuit configured to connect a first bit line (BLT) and a second bit line (BLF) shared by cells in said column, following reception of an erase signal (ERASE).

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