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    • 2. 发明申请
    • Loop control circuit for a data processor
    • 数据处理器的回路控制电路
    • US20060107028A1
    • 2006-05-18
    • US10536240
    • 2003-10-31
    • Patrick MeuwissenNur EnginCornelis Van BerkelMarco Bekooij
    • Patrick MeuwissenNur EnginCornelis Van BerkelMarco Bekooij
    • G06F9/44
    • G06F9/30181G06F9/325
    • A data processor (200) includes an operation execution unit (225) for executing instructions from an instruction memory (210) indicated by a program counter (220). A loop control circuit (230) stores respective associated loop information for a plurality of instruction loops in a register bank (232). The loop information includes at least an indication of an end of the loop and a loop count for indicating a number of times the loop should be executed. The loop control circuit (230) detects that one of the loops needs to be executed and in response to said detection, loads the loop information for the corresponding loop, and controls the program counter to execute the corresponding loop according to the loaded loop information. The loop information is initialized in response to a loop initialization instruction (240), where the initialization instruction is issued prior to and independent of a start of the loop initialized by the loop information.
    • 数据处理器(200)包括用于从由程序计数器(220)指示的指令存储器(210)执行指令的操作执行单元(225)。 环路控制电路(230)将用于多个指令循环的各个相关联的环路信息存储在寄存器组(232)中。 循环信息至少包括循环结束的指示和循环计数,用于指示应该执行循环的次数。 环路控制电路(230)检测到需要执行一个环路,并响应于所述检测,加载相应环路的环路信息,并根据加载的环路信息控制程序计数器执行相应的环路。 响应于循环初始化指令(240)初始化循环信息,其中初始化指令是在由循环信息初始化的循环的开始之前发出的。
    • 3. 发明申请
    • Address generation unit for a processor
    • 处理器的地址生成单元
    • US20060010255A1
    • 2006-01-12
    • US10515462
    • 2003-05-07
    • Cornelis Van BerkelPatrick Meuwissen
    • Cornelis Van BerkelPatrick Meuwissen
    • G06F3/00
    • G06T1/60G06F9/30043G06F15/8053
    • A processor includes a memory port for accessing a physical memory under control of an address. A processing unit executing instructions stored in the memory and/or operates on data stored in the memory. An address generation unit (“AGU”) generates address for controlling access to the memory; the AGU being associated with a plurality of N registers enabling the AGU to generate the address under control of an address generation mechanism. A memory unit is operative to save/load k of the N registers, where 2
    • 处理器包括用于在地址控制下访问物理存储器的存储器端口。 执行存储在存储器中的指令的处理单元和/或对存储在存储器中的数据进行操作。 地址生成单元(“AGU”)生成用于控制对存储器的访问的地址; AGU与多个N个寄存器相关联,使得AGU能够在地址生成机制的控制下生成地址。 一个存储器单元用于保存/加载N个寄存器的k,其中2 <= k <= N,由一个操作触发。 为此,存储器单元包括用于将k个寄存器与通过存储器端口写入存储器的一个存储器字连接的级联器,以及用于将从存储器读取的字通过存储器端口分离成k个寄存器的分离器。