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1. 发明申请

US20100097856A1 FLASH MEMORY AND ASSOCIATED METHODS 有权
标题翻译：闪存和相关方法
公开(公告)号：US20100097856A1
公开(公告)日：2010-04-22
申请号：US12643610
申请日：2009-12-21
申请人： Daniel Elmhurst , Giovanni Santin , Michele Incarnati , Violante Moschiano , Ercole Diiorio
发明人： Daniel Elmhurst , Giovanni Santin , Michele Incarnati , Violante Moschiano , Ercole Diiorio
IPC分类号： G11C16/04 , G11C7/06
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period.
摘要翻译：在一种操作方法中，与位线耦合的快闪存储器单元被编程，字线电压耦合到闪存单元，第一电压脉冲耦合到耦合在位线和在第一时间感测电容以将位线耦合到感测电容以产生指示闪存单元的状态的数据，第二电压脉冲在具有不同的第二大小的第二时间耦合到偏置晶体管并且第三电压脉冲在第三时间与具有与第二电压脉冲的第二幅度不同的第三幅度耦合到偏置晶体管。在一种操作方法中，第二电压脉冲在第一电压脉冲和第三电压脉冲在第二电压脉冲之后发生第二延迟时段之后的第一延迟时段，第二延迟周期不同于第一延迟周期。

2. 发明授权

US08391061B2 Flash memory and associated methods 有权
标题翻译：闪存和相关方法
公开(公告)号：US08391061B2
公开(公告)日：2013-03-05
申请号：US12643610
申请日：2009-12-21
申请人： Daniel Elmhurst , Giovanni Santin , Michele Incarnati , Violante Moschiano , Ercole Diiorio
发明人： Daniel Elmhurst , Giovanni Santin , Michele Incarnati , Violante Moschiano , Ercole Diiorio
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period.
摘要翻译：在一种操作方法中，与位线耦合的快闪存储器单元被编程，字线电压耦合到闪存单元，第一电压脉冲耦合到耦合在位线和在第一时间感测电容以将位线耦合到感测电容以产生指示闪存单元的状态的数据，第二电压脉冲在具有不同的第二大小的第二时间耦合到偏置晶体管并且第三电压脉冲在第三时间与具有与第二电压脉冲的第二幅度不同的第三幅度耦合到偏置晶体管。在一种操作方法中，第二电压脉冲在第一电压脉冲和第三电压脉冲在第二电压脉冲之后发生第二延迟时段之后的第一延迟时段，第二延迟周期不同于第一延迟周期。

3. 发明申请

US20080158986A1 FLASH MEMORY AND ASSOCIATED METHODS 审中-公开
标题翻译：闪存和相关方法
公开(公告)号：US20080158986A1
公开(公告)日：2008-07-03
申请号：US11618652
申请日：2006-12-29
申请人： Daniel Elmhurst , Giovanni Santin , Michele Incarnati , Violante Moschiano , Ercole Diiorio
发明人： Daniel Elmhurst , Giovanni Santin , Michele Incarnati , Violante Moschiano , Ercole Diiorio
IPC分类号： G11C16/28
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： In a method of operation, a flash memory cell is programmed, a word-line voltage is coupled to the flash memory cell, and a state of the flash memory cell is sensed at intervals to generate data to indicate a state of the flash memory cell. In a method of operation, a latch in a cache memory of a NAND flash memory is switched off, and the latch is initialized while the latch is switched off. A read voltage is coupled to a gate of a selected flash memory cell in the NAND flash memory where the selected flash memory cell is coupled to a bit-line, and the bit-line is coupled to an input of the latch while a voltage on the bit-line is changing.
摘要翻译：在一种操作方法中，闪存单元被编程，字线电压耦合到闪存单元，并且间隔地感测闪存单元的状态以产生数据以指示闪存单元的状态。在一种操作方法中，NAND闪存的高速缓冲存储器中的锁存器被关闭，并且在锁存器被关闭时初始化锁存器。读取电压耦合到NAND闪速存储器中所选择的快闪存储器单元的栅极，其中所选闪存单元耦合到位线，并且位线耦合到锁存器的输入，同时电压开位线正在改变。

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