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1. 发明授权

US08782302B2 Method and apparatus for routing transactions through partitions of a system-on-chip 有权
标题翻译：用于通过片上系统的分区路由事务的方法和装置
公开(公告)号：US08782302B2
公开(公告)日：2014-07-15
申请号：US13326991
申请日：2011-12-15
申请人： Ignazio Antonino Urzi , Philippe D'Audigier , Daniele Mangano
发明人： Ignazio Antonino Urzi , Philippe D'Audigier , Daniele Mangano
IPC分类号： G06F3/00 , G06F5/00 , G06F13/00
CPC分类号： G06F15/7842 , G06F15/7825
摘要： A node having a node input is configured to receive a plurality of transactions intended for a plurality of different targets. The node has multiple node outputs. At least one target is provided, that target including an input configured to receive a respective output of the node. The node is configured to direct transactions to the at least one target or an output (for passing to a different partition) depending on whether the transactions are intended for the target or a different target. This determination is made in response to a conversion operation which converts a target address of the transaction to an identification associated with the target or the output.
摘要翻译：具有节点输入的节点被配置为接收用于多个不同目标的多个事务。该节点具有多个节点输出。提供至少一个目标，该目标包括被配置为接收节点的相应输出的输入。该节点被配置为根据事务是针对目标还是不同的目标将事务定向到至少一个目标或输出（用于传递到不同的分区）。响应于将交易的目标地址转换为与目标或输出相关联的标识的转换操作进行该确定。

2. 发明授权

US08677045B2 Transaction reordering system and method with protocol indifference 有权
标题翻译：交易重新排序系统和方法与协议无差异
公开(公告)号：US08677045B2
公开(公告)日：2014-03-18
申请号：US13241874
申请日：2011-09-23
申请人： Daniele Mangano , Ignazio Antonino Urzi
发明人： Daniele Mangano , Ignazio Antonino Urzi
IPC分类号： G06F13/36 , G06F13/40
CPC分类号： G06F13/4059 , G06F13/1626 , G06F15/7825
摘要： An embodiment of a transaction reordering arrangement is provided. The transaction reordering arrangement includes a queue into which respective responses to requests are writable and a controller configured to control a position in said queue to which said respective responses to said requests are written. The position is controlled such that the responses are read out of said queue in an order which corresponds to an order in which the requests are issued.
摘要翻译：提供了交易重排序装置的实施例。交易重排序装置包括一个队列，对请求的各个响应可写入到该队列中;以及控制器，被配置为控制写入所述请求的所述各个响应的所述队列中的位置。控制位置使得响应以与发出请求的顺序相对应的顺序从所述队列中读出。

3. 发明授权

US08347258B2 Method and apparatus for interfacing multiple dies with mapping for source identifier allocation 有权
标题翻译：用于将多个管芯连接到用于源标识符分配的映射的方法和装置
公开(公告)号：US08347258B2
公开(公告)日：2013-01-01
申请号：US13028250
申请日：2011-02-16
申请人： Ignazio Antonino Urzi , Philippe D'Audigier , Olivier Sauvage , Stuart Ryan , Andrew Michael Jones
发明人： Ignazio Antonino Urzi , Philippe D'Audigier , Olivier Sauvage , Stuart Ryan , Andrew Michael Jones
IPC分类号： G06F17/50
CPC分类号： G09G5/006 , G06F3/14 , Y02T10/82
摘要： A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. This ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order.
摘要翻译：包装包括模具和至少一个另外的模具。管芯具有被配置为经由互连从另外的管芯接收事务请求并且经由互连将对事务请求的响应发送到所述另外管芯的接口。管芯还具有映射电路，其被配置为向接收到的事务分配本地源身份信息作为源身份信息，本地源身份信息包括一组可重用的本地源身份信息。这样可确保以相同原始来源身份和目标标记的事务的顺序，并允许以不同的源标识符标记的事务处理不正常。

4. 发明申请

US20120001668A1 DIE AND A PACKAGE COMPRISING A PLURALITY OF DIES 审中-公开
标题翻译： DIE和一个包含多个DIES的包装
公开(公告)号：US20120001668A1
公开(公告)日：2012-01-05
申请号：US13172421
申请日：2011-06-29
申请人： Ignazio Antonino Urzi , Philippe D'Audigier
发明人： Ignazio Antonino Urzi , Philippe D'Audigier
IPC分类号： H03L7/00
CPC分类号： G06F9/4843
摘要： A first die includes a controller configured to select at least one task to be performed by the first die and signal circuitry configured in response to the selection of the at least one task to provide a signal to be sent to a second die for initiating performance of at least one task on the second die which corresponds to (and is to be performed in a time coordinated manner with) the at least one task on the first die. The first die has task circuitry configured to perform the task in response to generation of the signal, and the second die has task circuitry configured to perform the corresponding task in response to receipt of the signal.
摘要翻译：第一管芯包括控制器，其被配置为选择要由第一管芯执行的至少一个任务和响应于对至少一个任务的选择而配置的信号电路，以提供要发送到第二管芯的信号，以启动性能所述第二管芯上的至少一个任务对应于所述第一管芯上的所述至少一个任务（并且将以时间协调的方式执行）。第一管芯具有被配置为响应于信号的产生执行任务的任务电路，并且第二管芯具有被配置为响应于该信号的接收而执行相应任务的任务电路。

5. 发明授权

US08521937B2 Method and apparatus for interfacing multiple dies with mapping to modify source identity 有权
标题翻译：用于将多个管芯连接到具有修改源标识的映射的方法和装置
公开(公告)号：US08521937B2
公开(公告)日：2013-08-27
申请号：US13028383
申请日：2011-02-16
申请人： Ignazio Antonino Urzi , Philippe D'Audigier , Olivier Sauvage , Stuart Ryan , Andrew Michael Jones
发明人： Ignazio Antonino Urzi , Philippe D'Audigier , Olivier Sauvage , Stuart Ryan , Andrew Michael Jones
IPC分类号： G06F13/14 , G06F13/38
CPC分类号： G06F13/385 , A01C7/04 , A01C7/20 , G06F15/173 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2924/12041 , H01L2924/15311 , H01L2924/00 , H01L2924/014
摘要： A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to receive the transaction request including at least first source identity information, wherein the first source identity information is associated with a source of the transaction request on the further die. The mapping circuitry is configured to modify the transaction request to replace the first source identity information with local source identity information, wherein that local source identity information is associated with the mapping circuitry. The mapping circuitry is configured to modify the received transaction request to provide said first source identity information in a further field.
摘要翻译：包装包括模具和至少一个另外的模具。管芯具有被配置为经由互连从另外的管芯接收事务请求并且经由互连将对事务请求的响应发送到所述另外管芯的接口。芯片还具有映射电路，其被配置为接收包括至少第一源标识信息的事务请求，其中第一源标识信息与另外裸片上的事务请求的源相关联。映射电路被配置为修改事务请求以用本地源标识信息替换第一源标识信息，其中本地源标识信息与映射电路相关联。映射电路被配置为修改所接收的事务请求以在另外的字段中提供所述第一源标识信息。

6. 发明申请

US20130061016A1 VERSATILE DATA PROCESSOR EMBEDDED IN A MEMORY CONTROLLER 审中-公开
标题翻译：嵌入在内存控制器中的多个数据处理器
公开(公告)号：US20130061016A1
公开(公告)日：2013-03-07
申请号：US13605880
申请日：2012-09-06
申请人： Ignazio Antonino Urzi , Nicolas Graciannette
发明人： Ignazio Antonino Urzi , Nicolas Graciannette
IPC分类号： G06F12/00 , G06F12/14
CPC分类号： G06F21/79
摘要： A first engine and a memory access controller are each configured to receive memory operation information in parallel. In response to receiving the memory operation information, the first engine is prepared to perform a function on memory data associated with the memory operation and the memory controller is configured to prepare the memory to cause the memory operation to be performed.
摘要翻译：第一引擎和存储器访问控制器各自被配置为并行地接收存储器操作信息。响应于接收到存储器操作信息，第一引擎准备执行与存储器操作相关联的存储器数据的功能，并且存储器控制器被配置为准备存储器以使得执行存储器操作。

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