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1. 发明申请

US20060125517A1 Techniques for optimizing design of a hard intellectual property block for data transmission 有权
标题翻译：用于优化硬件知识产权块设计数据传输的技术
公开(公告)号：US20060125517A1
公开(公告)日：2006-06-15
申请号：US11011543
申请日：2004-12-13
申请人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
发明人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
IPC分类号： H03K19/173 , G06F17/50 , H03K19/00 , G06F7/38
CPC分类号： H04L25/14
摘要： Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
摘要翻译：提供了用于为可编程逻辑集成电路上的HIP块中的数据传输接口实现信道对准的技术。 HIP块信道对准逻辑可以使用减少数量的并行数据路径来运行，这消耗了相当少的逻辑资源。此外，HIP块通道对准逻辑电路可以以较高的HIP内核时钟速率串行处理，减少锁定延迟时间。提供了用于在可编程逻辑电路中实现发送数据的错误处理的技术。可编程逻辑电路可以配置为实现为任何应用定制的错误生成和错误监视功能。或者，可以将逻辑元件配置为对不需要错误处理的应用执行其他功能。通过将时钟信号与数据信号一起路由到每个电路块来减少集成电路上的数据和时钟信号之间的相位偏移。

2. 发明授权

US07434192B2 Techniques for optimizing design of a hard intellectual property block for data transmission 有权
标题翻译：用于优化硬件知识产权块设计数据传输的技术
公开(公告)号：US07434192B2
公开(公告)日：2008-10-07
申请号：US11011543
申请日：2004-12-13
申请人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
发明人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
IPC分类号： G06F17/50 , G06F3/00 , G06F13/14 , H03K19/0175 , H03K19/177 , H01L25/00 , H04L12/46 , H04J3/06
CPC分类号： H04L25/14
摘要： Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
摘要翻译：提供了用于为可编程逻辑集成电路上的HIP块中的数据传输接口实现信道对准的技术。 HIP块信道对准逻辑可以使用减少数量的并行数据路径来运行，这消耗了相当少的逻辑资源。此外，HIP块通道对准逻辑电路可以以较高的HIP内核时钟速率串行处理，减少锁定延迟时间。提供了用于在可编程逻辑电路中实现发送数据的错误处理的技术。可编程逻辑电路可以配置为实现针对任何应用定制的错误生成和错误监视功能。或者，可以将逻辑元件配置为对不需要错误处理的应用执行其他功能。通过将时钟信号与数据信号一起路由到每个电路块来减少集成电路上的数据和时钟信号之间的相位偏移。

3. 发明授权

US07843216B2 Techniques for optimizing design of a hard intellectual property block for data transmission 有权
标题翻译：用于优化硬件知识产权块设计数据传输的技术
公开(公告)号：US07843216B2
公开(公告)日：2010-11-30
申请号：US12193532
申请日：2008-08-18
申请人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
发明人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H04L25/14
摘要： Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
摘要翻译：提供了用于为可编程逻辑集成电路上的HIP块中的数据传输接口实现信道对准的技术。 HIP块信道对准逻辑可以使用减少数量的并行数据路径来运行，这消耗了相当少的逻辑资源。此外，HIP块通道对准逻辑电路可以以较高的HIP内核时钟速率串行处理，减少锁定延迟时间。提供了用于在可编程逻辑电路中实现发送数据的错误处理的技术。可编程逻辑电路可以配置为实现为任何应用定制的错误生成和错误监视功能。或者，可以将逻辑元件配置为对不需要错误处理的应用执行其他功能。通过将时钟信号与数据信号一起路由到每个电路块来减少集成电路上的数据和时钟信号之间的相位偏移。

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