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1. 发明授权

US07242218B2 Techniques for combining volatile and non-volatile programmable logic on an integrated circuit 有权
标题翻译：在集成电路上组合易失性和非易失性可编程逻辑的技术
公开(公告)号：US07242218B2
公开(公告)日：2007-07-10
申请号：US11003586
申请日：2004-12-02
申请人： Rafael Camarota , Irfan Rahim , Boon Jin Ang , Thow Pang Chong
发明人： Rafael Camarota , Irfan Rahim , Boon Jin Ang , Thow Pang Chong
IPC分类号： H03K19/173 , H03K19/177 , G06F7/38 , H01L25/00
CPC分类号： G06F15/7867 , H03K19/17732 , H03K19/1776 , H03K19/17768 , H03K19/17772 , H03K19/17776
摘要： Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second block of programmable logic is configured by bits stored in off-chip memory. The function of IO banks on the IC is multiplexed between the two logic blocks of the IC. The programmable logic in the first block can be configured and fully functional in a fraction of the time that the programmable logic in the second block can be configured. The programmable logic in the first block can configure fast enough and have enough independence to assist in the configuration of the second block. The non-volatile memory can also provide security features to a user design, such as encryption.
摘要翻译：提供了将易失性和非易失性可编程逻辑组合到一个集成电路（IC）中的技术。 IC分为两部分。可编程逻辑的第一块由存储在片上非易失性存储器中的位来配置。可编程逻辑的第二块由存储在片外存储器中的位配置。 IC上的IO组的功能在IC的两个逻辑块之间复用。第一块中的可编程逻辑可以在可配置第二块中的可编程逻辑的几分之一时间内配置和完全运行。第一块中的可编程逻辑可以配置得足够快，并具有足够的独立性来辅助第二块的配置。非易失性存储器还可以为诸如加密的用户设计提供安全特征。

2. 发明授权

US08659334B2 Frequency control clock tuning circuitry 有权
标题翻译：频率控制时钟调谐电路
公开(公告)号：US08659334B2
公开(公告)日：2014-02-25
申请号：US13543724
申请日：2012-07-06
申请人： Teik Wah Lim , Eng Huat Lee , Ie Chen Chia , Thow Pang Chong , Boon Jin Ang , Kim Pin Tan
发明人： Teik Wah Lim , Eng Huat Lee , Ie Chen Chia , Thow Pang Chong , Boon Jin Ang , Kim Pin Tan
IPC分类号： H03L7/06
CPC分类号： H03L7/081 , G11C17/16 , G11C29/023 , G11C29/028 , G11C2029/4402 , H03L7/08
摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.
摘要翻译：公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合到控制块的多个可编程熔丝。所使用的可编程保险丝可能是一次性可编程（OTP）保险丝。控制块读取存储在可编程保险丝中的设置或数据。耦合到控制块的调谐电路接收由控制块发送的延迟。调谐电路允许调节IC而不改变制造掩模。调谐电路可以包括延迟链，以在需要时向IC提供额外的延迟，并且基于存储在可编程保险丝中并由控制块传输的延迟值来配置调谐电路中的延迟。

3. 发明申请

US20080297192A1 TECHNIQUES FOR OPTIMIZING DESIGN OF A HARD INTELLECTUAL PROPERTY BLOCK FOR DATA TRANSMISSION 有权
标题翻译：优化硬件知识产权块数据传输设计的技术
公开(公告)号：US20080297192A1
公开(公告)日：2008-12-04
申请号：US12193532
申请日：2008-08-18
申请人： Darren van WAGENINGEN , Curt WORTMAN , Boon-Jin ANG , Thow-Pang CHONG , Dan MANSUR , Ali BURNEY
发明人： Darren van WAGENINGEN , Curt WORTMAN , Boon-Jin ANG , Thow-Pang CHONG , Dan MANSUR , Ali BURNEY
IPC分类号： H03K19/0175 , H03K19/177 , H01L25/00 , H04L12/46 , H04J3/06
CPC分类号： H04L25/14
摘要： Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
摘要翻译：提供了用于为可编程逻辑集成电路上的HIP块中的数据传输接口实现信道对准的技术。 HIP块信道对准逻辑可以使用减少数量的并行数据路径来运行，这消耗了相当少的逻辑资源。此外，HIP块通道对准逻辑电路可以以较高的HIP内核时钟速率串行处理，减少锁定延迟时间。提供了用于在可编程逻辑电路中实现发送数据的错误处理的技术。可编程逻辑电路可以配置为实现为任何应用定制的错误生成和错误监视功能。或者，可以将逻辑元件配置为对不需要错误处理的应用执行其他功能。通过将时钟信号与数据信号一起路由到每个电路块来减少集成电路上的数据和时钟信号之间的相位偏移。

4. 发明授权

US08694944B1 Predicting routability of integrated circuits 有权
标题翻译：预测集成电路的可布线性
公开(公告)号：US08694944B1
公开(公告)日：2014-04-08
申请号：US12643528
申请日：2009-12-21
申请人： Sze Huey Soo , Thow Pang Chong , Boon Jin Ang , Kar Keng Chua
发明人： Sze Huey Soo , Thow Pang Chong , Boon Jin Ang , Kar Keng Chua
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/504 , G06F17/5054
摘要： Methods, computer program products, and systems are disclosed associated with calculating a routability metric for a second IC design using inputs from the compilation to a first IC design. The first and second IC designs are alternative implementation options for a user circuit design, such as FPGA and structured ASIC options. Information about user design demands on routing resources of one IC design are considered along with information about the projected supply of routing resources in another IC design, to produce a routing metric. The routing metric may be mapped to a degree of difficulty indicator, and either may be used to condition a compile of the user circuit to the second IC design or be used in other ways.
摘要翻译：公开了使用从汇编到第一IC设计的输入来计算第二IC设计的可路由度量的方法，计算机程序产品和系统。第一和第二IC设计是用户电路设计的替代实现选项，例如FPGA和结构化ASIC选项。关于一个IC设计的路由资源的用户设计需求的信息以及关于在另一个IC设计中的路由资源的预计供应的信息，以产生路由度量。路由度量可以映射到难度指标，并且可以用于将用户电路的编译调节到第二IC设计或以其他方式使用。

5. 发明申请

US20120274375A1 FREQUENCY CONTROL CLOCK TUNING CIRCUITRY 有权
标题翻译：频率控制时钟调谐电路
公开(公告)号：US20120274375A1
公开(公告)日：2012-11-01
申请号：US13543724
申请日：2012-07-06
申请人： Teik Wah Lim , Eng Huat Lee , Ie Chen Chia , Thow Pang Chong , Boon Jin Ang , Kim Pin Tan
发明人： Teik Wah Lim , Eng Huat Lee , Ie Chen Chia , Thow Pang Chong , Boon Jin Ang , Kim Pin Tan
IPC分类号： H03K3/86 , H03L7/06
CPC分类号： H03L7/081 , G11C17/16 , G11C29/023 , G11C29/028 , G11C2029/4402 , H03L7/08
摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.
摘要翻译：公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合到控制块的多个可编程熔丝。所使用的可编程保险丝可能是一次性可编程（OTP）保险丝。控制块读取存储在可编程保险丝中的设置或数据。耦合到控制块的调谐电路接收由控制块发送的延迟。调谐电路允许调节IC而不改变制造掩模。调谐电路可以包括延迟链，以在需要时向IC提供额外的延迟，并且基于存储在可编程保险丝中并由控制块传输的延迟值来配置调谐电路中的延迟。

6. 发明授权

US08232823B1 Frequency control clock tuning circuitry 有权
标题翻译：频率控制时钟调谐电路
公开(公告)号：US08232823B1
公开(公告)日：2012-07-31
申请号：US12479515
申请日：2009-06-05
申请人： Teik Wah Lim , Eng Huat Lee , Ie Chen Chia , Thow Pang Chong , Boon Jin Ang , Kim Pin Tan
发明人： Teik Wah Lim , Eng Huat Lee , Ie Chen Chia , Thow Pang Chong , Boon Jin Ang , Kim Pin Tan
IPC分类号： H03L7/06
CPC分类号： H03L7/081 , G11C17/16 , G11C29/023 , G11C29/028 , G11C2029/4402 , H03L7/08
摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.
摘要翻译：公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合到控制块的多个可编程熔丝。所使用的可编程保险丝可能是一次性可编程（OTP）保险丝。控制块读取存储在可编程保险丝中的设置或数据。耦合到控制块的调谐电路接收由控制块发送的延迟。调谐电路允许调节IC而不改变制造掩模。调谐电路可以包括延迟链，以在需要时向IC提供额外的延迟，并且基于存储在可编程保险丝中并由控制块传输的延迟值来配置调谐电路中的延迟。

7. 发明授权

US08037444B1 Programmable control of mask-programmable integrated circuit devices 有权
标题翻译：掩模可编程集成电路器件的可编程控制
公开(公告)号：US08037444B1
公开(公告)日：2011-10-11
申请号：US11490750
申请日：2006-07-20
申请人： Boon Jin Ang , Bee Yee Ng , Thow Pang Chong , Yu Fong Tan
发明人： Boon Jin Ang , Bee Yee Ng , Thow Pang Chong , Yu Fong Tan
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5054 , H03K19/173
摘要： An integrated circuit device such as a structured ASIC includes a mask-programmable portion and a post-fabrication-programmable portion. The mask-programmable portion includes circuitry that is able to read information from the post-fabrication-programmable portion and use that information to affect operation of other componentry of the mask-programmable portion. Signal timing is an example of the kind of operation that may be affected by the above-mentioned information, which may allow post-fabrication timing tuning of the device.
摘要翻译：诸如结构化ASIC的集成电路器件包括掩模可编程部分和后制造可编程部分。掩模可编程部分包括能够从后制造可编程部分读取信息并使用该信息来影响掩模可编程部分的其他部件的操作的电路。信号定时是可能受上述信息影响的操作种类的一个例子，这可能允许设备的制造后时序调谐。

8. 发明授权

US07843216B2 Techniques for optimizing design of a hard intellectual property block for data transmission 有权
标题翻译：用于优化硬件知识产权块设计数据传输的技术
公开(公告)号：US07843216B2
公开(公告)日：2010-11-30
申请号：US12193532
申请日：2008-08-18
申请人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
发明人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H04L25/14
摘要： Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
摘要翻译：提供了用于为可编程逻辑集成电路上的HIP块中的数据传输接口实现信道对准的技术。 HIP块信道对准逻辑可以使用减少数量的并行数据路径来运行，这消耗了相当少的逻辑资源。此外，HIP块通道对准逻辑电路可以以较高的HIP内核时钟速率串行处理，减少锁定延迟时间。提供了用于在可编程逻辑电路中实现发送数据的错误处理的技术。可编程逻辑电路可以配置为实现为任何应用定制的错误生成和错误监视功能。或者，可以将逻辑元件配置为对不需要错误处理的应用执行其他功能。通过将时钟信号与数据信号一起路由到每个电路块来减少集成电路上的数据和时钟信号之间的相位偏移。

9. 发明授权

US07683689B1 Delay circuit with delay cells in different orientations 有权
标题翻译：延迟电路具有不同方向的延迟单元
公开(公告)号：US07683689B1
公开(公告)日：2010-03-23
申请号：US12082296
申请日：2008-04-10
申请人： Tat Mun Lui , Kar Keng Chua , Boon Jin Ang , Thow Pang Chong , Kam Fai Suit
发明人： Tat Mun Lui , Kar Keng Chua , Boon Jin Ang , Thow Pang Chong , Kam Fai Suit
IPC分类号： H03H11/26
CPC分类号： H03K5/133
摘要： A delay circuit that includes a first delay cell oriented in a first orientation and a second delay cell oriented in a second orientation is described. In one embodiment, the first orientation is perpendicular to the second orientation. More specifically, in one embodiment, the first orientation is vertical and the second orientation is horizontal.
摘要翻译：描述了包括以第一取向取向的第一延迟单元和以第二取向定向的第二延迟单元的延迟电路。在一个实施例中，第一取向垂直于第二取向。更具体地，在一个实施例中，第一取向是垂直的，第二取向是水平的。

10. 发明授权

US07639047B1 Techniques for reducing clock skew in clock routing networks 有权
标题翻译：降低时钟路由网络时钟偏移的技术
公开(公告)号：US07639047B1
公开(公告)日：2009-12-29
申请号：US12053573
申请日：2008-03-22
申请人： Boon Jin Ang , Bee Yee Ng , Eng Huat Lee , Thow Pang Chong , Teng Kuan Koay
发明人： Boon Jin Ang , Bee Yee Ng , Eng Huat Lee , Thow Pang Chong , Teng Kuan Koay
IPC分类号： H03K19/00
CPC分类号： G06F1/10
摘要： A circuit includes a clock routing network. The clock routing network includes first and second clock paths. The first clock path routes a first clock signal to sub-circuits in the circuit. The first clock path has first buffers that buffer the first clock signal at the sub-circuits and first conductors in a first conductive layer of the circuit that transmit the first clock signal. The second clock path routes a second clock signal to the sub-circuits. The second clock path has second buffers that buffer the second clock signal at the sub-circuits, second conductors in the first conductive layer that transmit the second clock signal, and third conductors in a second conductive layer of the circuit. The second clock signal is routed through the third conductors at overlaps between the first clock path and the second clock path.
摘要翻译：电路包括时钟路由网络。时钟路由网络包括第一和第二时钟路径。第一时钟路径将第一时钟信号路由到电路中的子电路。第一时钟路径具有缓冲第一时钟信号在子电路处的第一缓冲器和传输第一时钟信号的电路的第一导电层中的第一导体。第二时钟路径将第二时钟信号路由到子电路。第二时钟路径具有缓冲子电路上的第二时钟信号的第二缓冲器，传输第二时钟信号的第一导电层中的第二导体和在该电路的第二导电层中的第三导体。第二时钟信号在第一时钟路径和第二时钟路径之间的重叠处被路由穿过第三导体。

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