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1. 发明申请

US20060125517A1 Techniques for optimizing design of a hard intellectual property block for data transmission 有权
标题翻译：用于优化硬件知识产权块设计数据传输的技术
公开(公告)号：US20060125517A1
公开(公告)日：2006-06-15
申请号：US11011543
申请日：2004-12-13
申请人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
发明人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
IPC分类号： H03K19/173 , G06F17/50 , H03K19/00 , G06F7/38
CPC分类号： H04L25/14
摘要： Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
摘要翻译：提供了用于为可编程逻辑集成电路上的HIP块中的数据传输接口实现信道对准的技术。 HIP块信道对准逻辑可以使用减少数量的并行数据路径来运行，这消耗了相当少的逻辑资源。此外，HIP块通道对准逻辑电路可以以较高的HIP内核时钟速率串行处理，减少锁定延迟时间。提供了用于在可编程逻辑电路中实现发送数据的错误处理的技术。可编程逻辑电路可以配置为实现为任何应用定制的错误生成和错误监视功能。或者，可以将逻辑元件配置为对不需要错误处理的应用执行其他功能。通过将时钟信号与数据信号一起路由到每个电路块来减少集成电路上的数据和时钟信号之间的相位偏移。

2. 发明授权

US07843216B2 Techniques for optimizing design of a hard intellectual property block for data transmission 有权
标题翻译：用于优化硬件知识产权块设计数据传输的技术
公开(公告)号：US07843216B2
公开(公告)日：2010-11-30
申请号：US12193532
申请日：2008-08-18
申请人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
发明人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H04L25/14
摘要： Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
摘要翻译：提供了用于为可编程逻辑集成电路上的HIP块中的数据传输接口实现信道对准的技术。 HIP块信道对准逻辑可以使用减少数量的并行数据路径来运行，这消耗了相当少的逻辑资源。此外，HIP块通道对准逻辑电路可以以较高的HIP内核时钟速率串行处理，减少锁定延迟时间。提供了用于在可编程逻辑电路中实现发送数据的错误处理的技术。可编程逻辑电路可以配置为实现为任何应用定制的错误生成和错误监视功能。或者，可以将逻辑元件配置为对不需要错误处理的应用执行其他功能。通过将时钟信号与数据信号一起路由到每个电路块来减少集成电路上的数据和时钟信号之间的相位偏移。

3. 发明授权

US07434192B2 Techniques for optimizing design of a hard intellectual property block for data transmission 有权
标题翻译：用于优化硬件知识产权块设计数据传输的技术
公开(公告)号：US07434192B2
公开(公告)日：2008-10-07
申请号：US11011543
申请日：2004-12-13
申请人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
发明人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
IPC分类号： G06F17/50 , G06F3/00 , G06F13/14 , H03K19/0175 , H03K19/177 , H01L25/00 , H04L12/46 , H04J3/06
CPC分类号： H04L25/14
摘要： Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
摘要翻译：提供了用于为可编程逻辑集成电路上的HIP块中的数据传输接口实现信道对准的技术。 HIP块信道对准逻辑可以使用减少数量的并行数据路径来运行，这消耗了相当少的逻辑资源。此外，HIP块通道对准逻辑电路可以以较高的HIP内核时钟速率串行处理，减少锁定延迟时间。提供了用于在可编程逻辑电路中实现发送数据的错误处理的技术。可编程逻辑电路可以配置为实现针对任何应用定制的错误生成和错误监视功能。或者，可以将逻辑元件配置为对不需要错误处理的应用执行其他功能。通过将时钟信号与数据信号一起路由到每个电路块来减少集成电路上的数据和时钟信号之间的相位偏移。

4. 发明申请

US20060114022A1 Output reporting techniques for hard intellectual property blocks 有权
标题翻译：硬性知识产权块的产出报告技术
公开(公告)号：US20060114022A1
公开(公告)日：2006-06-01
申请号：US11002577
申请日：2004-12-01
申请人： Darren van Wageningen , Curt Wortman
发明人： Darren van Wageningen , Curt Wortman
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17732 , H03K19/17792
摘要： Techniques for reducing the frequency of an output signal from a hard intellectual property (HIP) block on an integrated circuit are provided. By reducing the frequency of the output signal, circuit blocks in the integrated circuit that operate at a lower frequency than the HIP block are able to capture the output signal. A plurality of serially coupled flip-flops store values of an HIP output signal during each period of the output signal. Logic circuitry then generates a lower frequency HIP output signal in response to the values stored in the flip-flops. Also, a flip-flop can generate a heartbeat signal that is used to determine whether a signal within an HIP block is operating properly.
摘要翻译：提供了用于降低来自集成电路上的硬知识产权（HIP）块的输出信号的频率的技术。通过降低输出信号的频率，集成电路中以比HIP块低的频率工作的电路块能够捕获输出信号。多个串联耦合的触发器在输出信号的每个周期期间存储HIP输出信号的值。然后逻辑电路响应于存储在触发器中的值产生较低频率的HIP输出信号。此外，触发器可以产生用于确定HIP块内的信号是否正常工作的心跳信号。

5. 发明授权

US07801121B1 Serial communications systems with cyclic redundancy checking 有权
标题翻译：具有循环冗余校验的串行通信系统
公开(公告)号：US07801121B1
公开(公告)日：2010-09-21
申请号：US11407484
申请日：2006-04-20
申请人： Darren Van Wageningen , Curt Wortman
发明人： Darren Van Wageningen , Curt Wortman
IPC分类号： H04Q11/00
CPC分类号： H04Q11/04 , H04Q2213/13174 , H04Q2213/13215 , H04Q2213/13296 , H04Q2213/1332 , H04Q2213/13322
摘要： Integrated circuits such as programmable logic device integrated circuits are provided with transmitter and receiver circuitry for communicating over multi-lane serial communications links. Data is transmitted over the serial communications links in the form of data packets. Priority data packets may be nested within regular data packets. Regular data packets may be formed using start-of-packet and end-of-packet markers. The locations at which priority packets are nested within regular data packets may be denoted using suspend and continuation markers. A single cyclic redundancy check generator may be used to generate cyclic redundancy check words for the data packets. Start-of-packet markers, end-of-packet markers, suspend markers, continuation markers, and cyclic redundancy check words may be inserted and extracted from the serial communications link at fixed lane locations.
摘要翻译：诸如可编程逻辑器件集成电路的集成电路设置有用于在多通道串行通信链路上通信的发射机和接收机电路。数据以数据包的形式通过串行通信链路传输。优先级数据包可以嵌套在常规数据包中。可以使用数据包分组和分组结束标记来形成规则数据分组。优先分组嵌套在常规数据分组内的位置可以使用挂起和连续标记来表示。可以使用单个循环冗余校验生成器来生成数据分组的循环冗余校验字。可以在固定车道位置从串行通信链路插入和提取分组包起始标记，分组结束标记，挂起标记，连续标记和循环冗余校验字。

6. 发明授权

US07242217B2 Output reporting techniques for hard intellectual property blocks 有权
标题翻译：硬性知识产权块的产出报告技术
公开(公告)号：US07242217B2
公开(公告)日：2007-07-10
申请号：US11002577
申请日：2004-12-01
申请人： Darren van Wageningen , Curt Wortman
发明人： Darren van Wageningen , Curt Wortman
IPC分类号： H03K19/173 , H03K19/177 , H03K19/00 , G06F7/38 , H01L25/00
CPC分类号： H03K19/17736 , H03K19/17732 , H03K19/17792
摘要： Techniques for reducing the frequency of an output signal from a hard intellectual property (HIP) block on an integrated circuit are provided. By reducing the frequency of the output signal, circuit blocks in the integrated circuit that operate at a lower frequency than the HIP block are able to capture the output signal. A plurality of serially coupled flip-flops store values of an HIP output signal during each period of the output signal. Logic circuitry then generates a lower frequency HIP output signal in response to the values stored in the flip-flops. Also, a flip-flop can generate a heartbeat signal that is used to determine whether a signal within an HIP block is operating properly.
摘要翻译：提供了用于降低来自集成电路上的硬知识产权（HIP）块的输出信号的频率的技术。通过降低输出信号的频率，集成电路中以比HIP块低的频率工作的电路块能够捕获输出信号。多个串联耦合的触发器在输出信号的每个周期期间存储HIP输出信号的值。然后逻辑电路响应于存储在触发器中的值产生较低频率的HIP输出信号。此外，触发器可以产生用于确定HIP块内的信号是否正常工作的心跳信号。

7. 发明授权

US09531646B1 Multi-protocol configurable transceiver including configurable deskew in an integrated circuit 有权
标题翻译：多协议可配置收发器，包括集成电路中的可配置的偏移校正
公开(公告)号：US09531646B1
公开(公告)日：2016-12-27
申请号：US12632744
申请日：2009-12-07
申请人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee , Vinson Chan
发明人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee , Vinson Chan
IPC分类号： G06F3/00 , H04L12/861 , G06F5/10
CPC分类号： H04L49/90 , G06F5/10
摘要： Embodiments include a configurable multi-protocol transceiver including configurable deskew circuitry. In one embodiment, configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. In another embodiment, configurable circuitry is adapted to control a deskew character transmit insertion frequency. In another embodiment, a programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition. In another embodiment, configurable circuitry is adaptable to select between logic and routing resources in the transceiver and logic and routing resources in a core of the IC in which the transceiver is implemented for controlling at least certain deskew operations. In another embodiment, configurable selection circuitry allows deskew processing to occur in a data path either before or after clock compensation processing depending on a communication protocol for which the transceiver is to be configured.
摘要翻译：实施例包括可配置的多协议收发器，包括可配置的偏移电路。在一个实施例中，可配置电路适于控制多个缓冲器的允许数据深度。在另一个实施例中，可配置电路适于控制偏斜字符传输插入频率。在另一个实施例中，可编程状态机适于根据用于实现对准锁定状态的可选条件来控制读取和写入指针。在另一个实施例中，可配置电路适于在收发器中的逻辑和路由资源之间选择逻辑，并且在IC的核心中布线资源，其中实现收发器用于控制至少某些去歪斜操作。在另一个实施例中，可配置的选择电路允许在时钟补偿处理之前或之后在数据路径中进行偏移处理，这取决于要配置收发器的通信协议。

8. 发明授权

US09436250B1 Apparatus for improving power consumption of communication circuitry and associated methods 有权
标题翻译：用于改善通信电路和相关方法的功耗的装置
公开(公告)号：US09436250B1
公开(公告)日：2016-09-06
申请号：US13330635
申请日：2011-12-19
申请人： Curt Wortman , Keith Duwel , Michael Menghui Zheng
发明人： Curt Wortman , Keith Duwel , Michael Menghui Zheng
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： H03L7/0807 , G06F1/32 , G06F1/3278 , G06F1/3296 , G06F11/0736 , G06F11/076 , G06F11/079 , H03K19/0008 , H03K19/1737 , H03K19/17728 , H03K19/1776 , H04B17/309 , Y02D10/157
摘要： An integrated circuit (IC) includes communication circuitry, a body bias generator, and a controller. The communication circuitry includes a physical medium attachment (PMA) and a physical coding sublayer (PCS). The body bias generator provides body bias signals to the PMA and PCS. The controller controls the body bias generator such that the body bias signals are controlled to improve a power consumption of the communication circuitry.
摘要翻译：集成电路（IC）包括通信电路，体偏置发生器和控制器。通信电路包括物理介质连接（PMA）和物理编码子层（PCS）。身体偏置发生器向PMA和PCS提供身体偏置信号。控制器控制身体偏置发生器，使得身体偏置信号被控制以提高通信电路的功率消耗。

9. 发明授权

US08949493B1 Configurable multi-lane scrambler for flexible protocol support 有权
标题翻译：可配置的多通道加扰器，用于灵活的协议支持
公开(公告)号：US08949493B1
公开(公告)日：2015-02-03
申请号：US12847761
申请日：2010-07-30
申请人： Curt Wortman , Chong H. Lee , Huy Ngo
发明人： Curt Wortman , Chong H. Lee , Huy Ngo
IPC分类号： G06F3/00 , G06F13/00 , G06F5/00 , G06F13/12 , G06M3/00 , G11C19/00 , G01R31/28 , G06F17/50 , G06F1/02 , G06F7/58 , H04L9/00
CPC分类号： H04L25/03866 , G06F3/00 , G06F5/00 , G06F7/58 , G06F13/00 , G06F13/12 , G06F13/40 , G06F13/4221 , G06F13/4282 , G11C7/1012 , G11C7/1036 , G11C19/00 , G11C19/285 , H04L9/00
摘要： Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.
摘要翻译：公开了与可配置加扰电路相关的各种结构和方法。实施例可以被配置为支持多个协议中的一个。一些实施例涉及可配置的多径扰频器，其可以适于组合跨越多个车道的加扰电路或者提供独立的基于车道的加扰器。一些实施例可配置为选择加扰器类型。一些实施例可配置为适应多个协议特定的加扰多项式之一。一些实施例涉及在数据的最低有效位（“LSB”）和最高有效位（“MSB”）排序之间进行选择。在一些实施例中，每个通道中的加扰器电路适于处理超过一位宽的数据。

10. 发明授权

US08650447B1 Apparatus and methods for controlled error injection 有权
标题翻译：用于控制误差注入的装置和方法
公开(公告)号：US08650447B1
公开(公告)日：2014-02-11
申请号：US13183147
申请日：2011-07-14
申请人： Curt Wortman , Keith Duwel , Huy Ngo
发明人： Curt Wortman , Keith Duwel , Huy Ngo
IPC分类号： G01R31/28 , G01R27/28 , G01R31/00 , G01R31/14 , G11C7/00 , G11C29/00
CPC分类号： G11C29/54 , G01R31/318516 , G11C29/04
摘要： In accordance with an embodiment of the invention, precision control of error injection may be accomplished by way of synchronous error signals accompanying data transfers along various pipeline stages of a data path. The synchronous error signals may be used to trigger error events in a given protocol logic block (i.e. in a given sub-component of the data path). The protocol logic block is configurable to determine whether any action is to be taken upon the assertion of the error signal. Multiple error events may be triggered as the data signal (and its accompanying synchronous error signal) passes through pipelined functions of the data path so as to create complex error conditions. In addition, deterministic handling of created errors may be accomplished using a loopback path with bypassable blocks on both forward and reverse transformations. Other embodiments, aspects and features are also disclosed.
摘要翻译：根据本发明的实施例，错误注入的精确控制可以通过伴随数据路径的各个流水线级数据传输的同步误差信号来实现。同步误差信号可用于触发给定协议逻辑块（即在数据路径的给定子组件中）的错误事件。协议逻辑块是可配置的，以确定是否在断言错误信号时采取任何动作。随着数据信号（及其伴随的同步误差信号）通过数据路径的流水线功能，可能会触发多个错误事件，从而创建复杂的错误条件。此外，可以使用在正向和反向转换两者上具有可旁路块的环回路径来实现所创建的错误的确定性处理。还公开了其它实施例，方面和特征。

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