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1. 发明授权

US5590292A Scalable tree structured high speed input/output subsystem architecture 失效
标题翻译：可扩展树结构高速输入/输出子系统架构
公开(公告)号：US5590292A
公开(公告)日：1996-12-31
申请号：US7333
申请日：1993-01-21
申请人： David R. Wooten , Craig A. Miller , Kevin B. Leigh , Robert B. Costley , Christopher E. Simonich
发明人： David R. Wooten , Craig A. Miller , Kevin B. Leigh , Robert B. Costley , Christopher E. Simonich
IPC分类号： G06F13/40 , G06F13/36 , G06F15/17
CPC分类号： G06F13/4022
摘要： A point to point connection architecture for a computer I/O subsystem, resulting in a scalable tree structure. A Master I/O Concentrator (MIOC) is connected to the host bus and handles conversion between a bus oriented structure and the tree structure of the I/O subsystem. Ports away from the host bus are downstream ports and conform to a simple byte wide message protocol. Various IOCs and devices can be attached to one of the downstream ports on the MIOC. The MIOC directs transmissions to the appropriate channel based on a geographical addressing scheme. The IOC connections act as further points of branching. Ultimately IOD or I/O devices are reached, having an upstream port for connection to the IOC and a downstream port and internal logic appropriate for the particular peripheral device. Various registers are present in the IOCs and the IODs to allow determination of the topology and particular devices present. Messages and commands are transferred in the I/O subsystem in defined packets. Various read, write and exchange commands are used, with a read response being utilized to allow split transaction read operations. Certain status and control commands are also present. Interrupts are handled by having the interrupt levels correspond to memory addresses of the programmable interrupt controller, thus allowing simple selection of interrupts to be generated by the devices and no need for separate wiring.
摘要翻译：用于计算机I / O子系统的点对点连接架构，从而产生可扩展的树结构。主I / O集中器（MIOC）连接到主机总线，处理面向总线的结构与I / O子系统的树结构之间的转换。远离主机总线的端口是下游端口，符合简单的字节宽消息协议。各种IOC和设备可以连接到MIOC的下游端口之一。 MIOC根据地理寻址方案将传输指向适当的信道。 IOC连接充当分支的进一步点。最终达到IOD或I / O设备，具有用于连接到IOC的上行端口和下游端口以及适用于特定外围设备的内部逻辑。各种寄存器存在于IOC和IOD中，以允许确定拓扑和存在的特定设备。消息和命令在I / O子系统中以定义的数据包传输。使用各种读取，写入和交换命令，其中使用读取响应来允许分离事务读取操作。还存在某些状态和控制命令。中断通过使中断电平对应于可编程中断控制器的存储器地址来处理，从而允许简单地选择要由器件产生的中断，而不需要单独的布线。

2. 发明授权

US5687388A Scalable tree structured high speed input/output subsystem architecture 失效
标题翻译：可扩展树结构高速输入/输出子系统架构
公开(公告)号：US5687388A
公开(公告)日：1997-11-11
申请号：US986918
申请日：1992-12-08
申请人： David R. Wooten , Craig A. Miller , Kevin B. Leigh , Robert Brett Costley , Christopher E. Simonich
发明人： David R. Wooten , Craig A. Miller , Kevin B. Leigh , Robert Brett Costley , Christopher E. Simonich
IPC分类号： G06F13/40 , G06F13/14 , G06F13/00
CPC分类号： G06F13/4022
摘要： A point to point connection architecture for a computer I/O subsystem, resulting in a scalable tree structure. A Master I/O Concentrator (MIOC) is connected to the host bus and handles conversion between a bus oriented structure and the tree structure of the I/O subsystem. Ports away from the host bus are downstream ports and conform to a simple byte wide message protocol. Various IOCs and devices can be attached to one of the downstream ports on the MIOC. The MIOC directs transmissions to the appropriate channel based on a geographical addressing scheme. The IOC connections act as further points of branching. Ultimately IOD or I/O devices are reached, having an upstream port for connection to the IOC and a downstream port and internal logic appropriate for the particular peripheral device. Various registers are present in the IOCs and the IODs to allow determination of the topology and particular devices present. Messages and commands are transferred in the I/O subsystem in defined packets. Various read, write and exchange commands are used, with a read response being utilized to allow split transaction read operations. Certain status and control commands are also present. Interrupts are handled by having the interrupt levels correspond to memory addresses of the programmable interrupt controller, thus allowing simple selection of interrupts to be generated by the devices and no need for separate wiring.
摘要翻译：用于计算机I / O子系统的点对点连接架构，从而产生可扩展的树结构。主I / O集中器（MIOC）连接到主机总线，处理面向总线的结构与I / O子系统的树结构之间的转换。远离主机总线的端口是下游端口，符合简单的字节宽消息协议。各种IOC和设备可以连接到MIOC的下游端口之一。 MIOC根据地理寻址方案将传输指向适当的信道。 IOC连接充当分支的进一步点。最终达到IOD或I / O设备，具有用于连接到IOC的上行端口和下游端口以及适用于特定外围设备的内部逻辑。各种寄存器存在于IOC和IOD中，以允许确定拓扑和存在的特定设备。消息和命令在I / O子系统中以定义的数据包传输。使用各种读取，写入和交换命令，其中使用读取响应来允许拆分事务读取操作。还存在某些状态和控制命令。中断通过使中断电平对应于可编程中断控制器的存储器地址来处理，从而允许简单地选择要由器件产生的中断，而不需要单独的布线。

3. 发明授权

US06256744B1 Personal computer component signal line isolation for an auxiliary powered component 有权
标题翻译：用于辅助动力部件的个人计算机部件信号线隔离
公开(公告)号：US06256744B1
公开(公告)日：2001-07-03
申请号：US09158962
申请日：1998-09-21
申请人： Christopher E. Simonich , Robin T. Tran
发明人： Christopher E. Simonich , Robin T. Tran
IPC分类号： G06F126
CPC分类号： G06F1/263
摘要： In a personal computer system utilizing both a main power supply and an auxiliary power supply, the input and output signal lines of auxiliary powered components are selectively isolated from components powered solely by the main power supply. Gating circuitry and buffer circuitry, controlled by various enable signals, are used to isolate the signal lines. External pull-down or pull-up resistors are no longer required, which frees up printed circuit board area for other components and conserves board space in the computer system.
摘要翻译：在利用主电源和辅助电源的个人计算机系统中，辅助供电部件的输入和输出信号线与由主电源单独供电的部件选择性地隔离。由各种使能信号控制的门控电路和缓冲电路用于隔离信号线。外部下拉或上拉电阻不再需要，这为其他组件释放了印刷电路板区域，并节省了计算机系统中的电路板空间。

4. 发明授权

US06199123B1 Computer system for supporting increased PCI master devices without the requiring additional bridge chips 失效
标题翻译：用于支持增加PCI主设备的计算机系统，无需额外的桥接芯片
公开(公告)号：US06199123B1
公开(公告)日：2001-03-06
申请号：US09126110
申请日：1998-07-30
申请人： Christopher E. Simonich , Robin T. Tran
发明人： Christopher E. Simonich , Robin T. Tran
IPC分类号： G06F1314
CPC分类号： G06F13/364
摘要： A PCI-based computer system is provided with an expanded number of PCI master devices, in effect a second level of PCI arbitration. The expansion is made available without requiring additional bridge chips. Multiple PCI devices may arbitrate for control of the PCI bus via the primary PCI bus controller without requiring a specifically assigned signal pair, yet appear to system software to reside on the primary PCI bus.
摘要翻译：基于PCI的计算机系统具有扩展数量的PCI主设备，实际上是PCI仲裁的第二级。扩展可用，无需额外的桥芯片。多个PCI设备可以经由主PCI总线控制器仲裁用于PCI总线的控制，而不需要专门分配的信号对，但是对系统软件显示为驻留在主PCI总线上。

5. 发明授权

US6145085A Method and apparatus for providing remote access to security features on a computer network 失效
标题翻译：用于提供对计算机网络上的安全特征的远程访问的方法和装置
公开(公告)号：US6145085A
公开(公告)日：2000-11-07
申请号：US070458
申请日：1998-04-30
申请人： Robin T. Tran , Christopher E. Simonich
发明人： Robin T. Tran , Christopher E. Simonich
IPC分类号： G06F21/00 , H04L9/32
CPC分类号： G06F21/31
摘要： A run-time security methodology and apparatus for supporting complete access to the security features of a network computer by a network administrator. In a network computer according to the invention, various resources are secured by a security device. The resources are accessible by a computer user with knowledge of one or more user passwords stored in the security device. An administrator password is also stored in the security device. In addition to control access to specified resources, the administrator password also functions as a surrogate for the other passwords stored in the security device. An administrator password implemented according to the invention thereby allows a network administrator to remotely override any activated user security settings and receive complete access to a secured network computer.
摘要翻译：用于支持由网络管理员完全访问网络计算机的安全特征的运行时安全方法和装置。在根据本发明的网络计算机中，各种资源由安全装置保护。资源可以由具有存储在安全设备中的一个或多个用户密码的知识的计算机用户访问。管理员密码也存储在安全设备中。除了控制对指定资源的访问之外，管理员密码还用作存储在安全设备中的其他密码的代理。根据本发明实施的管理员密码从而允许网络管理员远程覆盖任何激活的用户安全设置并接收对安全网络计算机的完整访问。

6. 发明授权

US06138240A Secure general purpose input/output pins for protecting computer system resources 失效
标题翻译：用于保护计算机系统资源的安全通用输入/输出引脚
公开(公告)号：US06138240A
公开(公告)日：2000-10-24
申请号：US100452
申请日：1998-06-19
申请人： Robin T. Tran , Christopher E. Simonich
发明人： Robin T. Tran , Christopher E. Simonich
IPC分类号： G06F21/00 , G06F11/00
CPC分类号： G06F21/82
摘要： A security device and methodology that prevents unauthorized access to general purpose I/O pins in a computer system. In a system according to the invention, secure general purpose I/O pins are utilized as enable signals for data transfer devices such as Universal Serial Port (USB) ports. In one embodiment of the invention, access to the secure general purpose I/O pins is governed by an administrator password that is protected by a memory slot in a security device. When an administrator (or other authorized user) desires access to the general purpose I/O register that controls the secure general purpose I/O pins, the administrator enters the administrator password. If the password is correct, the relevant slot of the security device is unlocked, thereby permitting completion of write cycles to the secure general purpose I/O register. If a write cycle to the secure general purpose I/O register is attempted while the relevant slot in the security device is locked, the write cycle is ignored. Control and monitoring of various system resources in a secure manner is thereby permitted via use of the secure general purpose I/O pins.
摘要翻译：防止未经授权访问计算机系统中通用I / O引脚的安全设备和方法。在根据本发明的系统中，安全通用I / O引脚被用作诸如通用串行端口（USB）端口的数据传输设备的使能信号。在本发明的一个实施例中，对安全通用I / O引脚的访问受由安全设备中的存储器插槽保护的管理员密码的控制。管理员（或其他授权用户）希望访问控制安全通用I / O引脚的通用I / O寄存器时，管理员输入管理员密码。如果密码正确，则安全设备的相关插槽被解锁，从而允许完成到安全通用I / O寄存器的写周期。如果在安全设备中的相关插槽被锁定时尝试向安全通用I / O寄存器写入周期，则忽略写入周期。从而可以通过使用安全的通用I / O引脚来以安全的方式控制和监视各种系统资源。

7. 发明授权

US06301665B1 Security methodology for devices having plug and play capabilities 失效
标题翻译：具有即插即用功能的设备的安全方法
公开(公告)号：US06301665B1
公开(公告)日：2001-10-09
申请号：US09070457
申请日：1998-04-30
申请人： Christopher E. Simonich , Robin T. Tran
发明人： Christopher E. Simonich , Robin T. Tran
IPC分类号： G06F1214
CPC分类号： G06F21/79
摘要： A security methodology and security logic for protecting Plug and Play computer system components from unauthorized access. The security logic prevents modification of the base addresses of specified Plug and Play computer system components by blocking writes to specific index locations programmed into security registers. In the disclosed embodiment of the invention, the base address of a Super I/O chip is protected, as well as the base addresses of specified logical devices in the Super I/O chip. Protecting the base addresses in this manner prevents the security logic from being circumvented by interfering with the address decoding used to track reads and writes to protected index registers. In addition, the security registers are programmed to prevent access to the protected index registers of the logical devices.
摘要翻译：用于保护即插即用计算机系统组件免受未经授权的访问的安全方法和安全逻辑。安全逻辑防止通过阻止对编程到安全寄存器中的特定索引位置的写入来修改指定的即插即用计算机系统组件的基址。在本发明所公开的实施例中，超级I / O芯片的基地址以及超级I / O芯片中指定的逻辑设备的基址被保护。以这种方式保护基地址可防止通过干扰用于跟踪对受保护的索引寄存器的读取和写入的地址解码来避免安全逻辑。此外，安全寄存器被编程以防止访问逻辑设备的受保护的索引寄存器。

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