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1. 发明授权

US08279886B2 Dataport and methods thereof 有权
标题翻译：数据端口及其方法
公开(公告)号：US08279886B2
公开(公告)日：2012-10-02
申请号：US11024909
申请日：2004-12-30
申请人： Dinakar Munagala , Hong Jiang , Bishara Shomar , Val Cook , Michael K. Dwyer , Thomas Piazza
发明人： Dinakar Munagala , Hong Jiang , Bishara Shomar , Val Cook , Michael K. Dwyer , Thomas Piazza
IPC分类号： H04L12/28
CPC分类号： G06F13/1668
摘要： A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.
摘要翻译：无上下文（无状态）数据端口可能允许多个处理器对共享内存执行读写操作。操作可以包括例如诸如图像和视频操作的结构化数据操作。数据端口可以执行与块存储器操作相关联的寻址计算。因此，数据端口可能能够例如从其责任中减轻其服务的处理器。可以使用可以以标准和一般化方式实现的消息接口来访问数据端口，并且因此可以容易地在不同类型的处理器之间传送。

2. 发明申请

US20060146852A1 Dataport and methods thereof 有权
标题翻译：数据端口及其方法
公开(公告)号：US20060146852A1
公开(公告)日：2006-07-06
申请号：US11024909
申请日：2004-12-30
申请人： Dinakar Munagala , Hong Jiang , Bishara Shomar , Val Cook , Michael Dwyer , Thomas Piazza
发明人： Dinakar Munagala , Hong Jiang , Bishara Shomar , Val Cook , Michael Dwyer , Thomas Piazza
IPC分类号： H04L12/28
CPC分类号： G06F13/1668
摘要： A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.
摘要翻译：无上下文（无状态）数据端口可能允许多个处理器对共享内存执行读写操作。操作可以包括例如诸如图像和视频操作的结构化数据操作。数据端口可以执行与块存储器操作相关联的寻址计算。因此，数据端口可能能够例如从其责任中减轻其服务的处理器。可以使用可以以标准和一般化方式实现的消息接口来访问数据端口，并且因此可以容易地在不同类型的处理器之间传送。

3. 发明申请

US20090327661A1 MECHANISMS TO HANDLE FREE PHYSICAL REGISTER IDENTIFIERS FOR SMT OUT-OF-ORDER PROCESSORS 审中-公开
标题翻译：用于SMT订单处理器的免费物理寄存器识别器的机制
公开(公告)号：US20090327661A1
公开(公告)日：2009-12-31
申请号：US12165186
申请日：2008-06-30
申请人： Zeev Sperber , David J. Sager , Fernando Latorre , Ori Lempel , Evgeni Krimer , Bishara Shomar
发明人： Zeev Sperber , David J. Sager , Fernando Latorre , Ori Lempel , Evgeni Krimer , Bishara Shomar
IPC分类号： G06F9/305
CPC分类号： G06F9/3851 , G06F9/30098 , G06F9/384 , G06F9/3885
摘要： Methods and apparatus relating to mechanisms to handle free physical register identifiers for SMT (Simultaneous Multi-Threading) out-of-order processors are described. In some embodiments, a physical register file stores both speculative data and architectural data corresponding to a plurality of registers. A free list logic may maintain free physical register identifiers corresponding to the plurality of registers. An instruction may read the architectural data from the physical register file at dispatch. Other embodiments are also described and claimed.
摘要翻译：描述了用于处理SMT（同时多线程）无序处理器的免费物理寄存器标识符的机制的方法和装置。在一些实施例中，物理寄存器文件存储对应于多个寄存器的推测数据和架构数据。空闲列表逻辑可以保持与多个寄存器对应的空闲物理寄存器标识符。指令可以在调度时从物理寄存器文件读取架构数据。还描述和要求保护其他实施例。

4. 发明授权

US06697933B1 Method and apparatus for fast, speculative floating point register renaming 有权
标题翻译：用于快速，推测浮点寄存器重命名的方法和装置
公开(公告)号：US06697933B1
公开(公告)日：2004-02-24
申请号：US09539221
申请日：2000-03-30
申请人： Gregory Pribush , Ronny Ronen , Bishara Shomar
发明人： Gregory Pribush , Ronny Ronen , Bishara Shomar
IPC分类号： G06F930
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： According to one aspect of the invention, a method is provided in which a current instance of an instruction is received. The current instance of the instruction contains a reference to a logical floating point register. A first rename phase is performed to convert the current's instance reference to the logical floating point register into a reference to an absolute register. A second rename phase is performed in parallel with the first rename phase to convert the reference to the absolute register into a reference to a physical register, based upon results obtained from performing the first rename phase with respect to a previous instance of the instruction.
摘要翻译：根据本发明的一个方面，提供一种接收指令的当前实例的方法。指令的当前实例包含对逻辑浮点寄存器的引用。执行第一重命名阶段以将当前的实例引用转换为逻辑浮点寄存器，以引用到绝对寄存器。与第一重命名阶段并行地执行第二重命名阶段，以基于相对于先前的指令实例执行第一重命名阶段获得的结果，将对绝对寄存器的引用转换为对物理寄存器的引用。

5. 发明授权

US06601155B2 Hot way caches: an energy saving technique for high performance caches 有权
标题翻译：热门缓存：高性能缓存的节能技术
公开(公告)号：US06601155B2
公开(公告)日：2003-07-29
申请号：US09823170
申请日：2001-03-29
申请人： Evgeni Krimer , Bishara Shomar , Ronny Ronen
发明人： Evgeni Krimer , Bishara Shomar , Ronny Ronen
IPC分类号： G06F1208
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： A device is presented including a processor. A local memory is connected to the processor. The processor includes a hot way cache accessing process. A method is presented that includes accessing a memory. The method includes processing a first plurality of memory cells and a second plurality of memory cells in the memory. The method determines if a memory block is a last recently accessed memory block. The method determines whether a memory block accessed is a hit or a miss. The method accesses a lower memory level if the memory block accessed is a miss. Also, processing the second plurality of memory cells for an exact block if the block accessed is a hit but not the last recently accessed memory block. And, providing the memory block for additional access if the memory block accessed is a hit and is a last recently accessed memory block.
摘要翻译：呈现包括处理器的设备。本地存储器连接到处理器。处理器包括热路缓存访问过程。提出了一种包括访问存储器的方法。该方法包括处理存储器中的第一多个存储单元和第二多个存储单元。该方法确定存储器块是否是最近最近访问的存储器块。该方法确定访问的存储器块是否是命中或未命中。如果访问的存储器块是错误的，该方法访问较低的存储器级别。此外，如果访问的块是命中而不是最近最近访问的存储器块，则处理第二多个存储器单元用于精确块。并且，如果访问的存储器块是命中并且是最后最近访问的存储器块，则提供用于附加访问的存储器块。

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