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1. 发明授权

US08279886B2 Dataport and methods thereof 有权
标题翻译：数据端口及其方法
公开(公告)号：US08279886B2
公开(公告)日：2012-10-02
申请号：US11024909
申请日：2004-12-30
申请人： Dinakar Munagala , Hong Jiang , Bishara Shomar , Val Cook , Michael K. Dwyer , Thomas Piazza
发明人： Dinakar Munagala , Hong Jiang , Bishara Shomar , Val Cook , Michael K. Dwyer , Thomas Piazza
IPC分类号： H04L12/28
CPC分类号： G06F13/1668
摘要： A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.
摘要翻译：无上下文（无状态）数据端口可能允许多个处理器对共享内存执行读写操作。操作可以包括例如诸如图像和视频操作的结构化数据操作。数据端口可以执行与块存储器操作相关联的寻址计算。因此，数据端口可能能够例如从其责任中减轻其服务的处理器。可以使用可以以标准和一般化方式实现的消息接口来访问数据端口，并且因此可以容易地在不同类型的处理器之间传送。

2. 发明申请

US20060146852A1 Dataport and methods thereof 有权
标题翻译：数据端口及其方法
公开(公告)号：US20060146852A1
公开(公告)日：2006-07-06
申请号：US11024909
申请日：2004-12-30
申请人： Dinakar Munagala , Hong Jiang , Bishara Shomar , Val Cook , Michael Dwyer , Thomas Piazza
发明人： Dinakar Munagala , Hong Jiang , Bishara Shomar , Val Cook , Michael Dwyer , Thomas Piazza
IPC分类号： H04L12/28
CPC分类号： G06F13/1668
摘要： A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.
摘要翻译：无上下文（无状态）数据端口可能允许多个处理器对共享内存执行读写操作。操作可以包括例如诸如图像和视频操作的结构化数据操作。数据端口可以执行与块存储器操作相关联的寻址计算。因此，数据端口可能能够例如从其责任中减轻其服务的处理器。可以使用可以以标准和一般化方式实现的消息接口来访问数据端口，并且因此可以容易地在不同类型的处理器之间传送。

3. 发明申请

US20060149938A1 Determining a register file region based at least in part on a value in an index register 审中-公开
标题翻译：至少部分地基于索引寄存器中的值来确定寄存器文件区域
公开(公告)号：US20060149938A1
公开(公告)日：2006-07-06
申请号：US11025105
申请日：2004-12-29
申请人： Hong Jiang , Val Cook , Thomas Piazza , Michael Dwyer
发明人： Hong Jiang , Val Cook , Thomas Piazza , Michael Dwyer
IPC分类号： G06F15/00
CPC分类号： G06F9/30167 , G06F9/30036 , G06F9/30098 , G06F9/3016 , G06F9/3455 , G06F9/355 , G06F9/3885
摘要： According to some embodiments, a value is retrieved from a location in an index register. A region in a register file may then be determined based at least in part on the value. Information may then be stored into the determined region of the register file.
摘要翻译：根据一些实施例，从索引寄存器中的位置检索值。然后可以至少部分地基于该值来确定寄存器文件中的区域。然后，信息可以被存储到寄存器文件的确定区域中。

4. 发明申请

US20060139366A1 Efficient Z testing 有权
标题翻译：高效Z测试
公开(公告)号：US20060139366A1
公开(公告)日：2006-06-29
申请号：US11023639
申请日：2004-12-29
申请人： Thomas Piazza , Eric Samson , Nasseh Akaaboune , Dinakar Munagala
发明人： Thomas Piazza , Eric Samson , Nasseh Akaaboune , Dinakar Munagala
IPC分类号： G09G5/02
CPC分类号： G06T15/405
摘要： Z testing during computer graphics rendering is performed in a manner so as to optimize rendering. The status of a pixel as non-promotable may be tracked using a pixel status array (PSA). Each PSA row may contain bits which correspond to the non-promotable status of pixels. Each row may include five pixels, the first four of which represent the pixels in a subspan. If the row corresponds to a valid subspan, a determination may be made as to whether any pixel in the subspan is represented by a one, indicating that the pixel is non-promotable. This row corresponds to a previous subspan that has been sent down rendering pipeline. If a one is present, then the current subspan may be stalled until the pixels of the previous subspan has gone through color calculation. If, in the row that has just been read, no pixels are represented by a one, then a determination may be made as to whether any pixels in the current subspan are non-promotable. If so, then the corresponding bit in the current PSA row may be set to one. Otherwise, the Z test may be performed on each pixel of the current subspan.
摘要翻译：在计算机图形渲染期间的Z测试以优化渲染的方式执行。可以使用像素状态阵列（PSA）跟踪不可升级的像素的状态。每个PSA行可以包含对应于像素的不可升级状态的位。每行可以包括五个像素，其中前四个表示子跨距中的像素。如果该行对应于有效的子跨度，则可以确定子跨越中的任何像素是否由一个表示，表示该像素是不可升级的。此行对应于已向下渲染管道发送的先前子跨。如果存在一个，那么当前的子跨越可能会停顿，直到前一个子跨越的像素经过颜色计算。如果在刚刚读取的行中没有像素由一个像素表示，则可以确定当前子跨距中的任何像素是否不可升级。如果是，则当前PSA行中的相应位可以被设置为1。否则，可以对当前子跨的每个像素执行Z测试。

5. 发明授权

US08072451B2 Efficient Z testing 有权
标题翻译：高效Z测试
公开(公告)号：US08072451B2
公开(公告)日：2011-12-06
申请号：US11023639
申请日：2004-12-29
申请人： Thomas Piazza , Eric Samson , Nasseh Akaaboune , Dinakar Munagala
发明人： Thomas Piazza , Eric Samson , Nasseh Akaaboune , Dinakar Munagala
IPC分类号： G06T15/40 , G09G5/02 , G09G5/36
CPC分类号： G06T15/405
摘要： Z testing during computer graphics rendering is performed in a manner so as to optimize rendering. The status of a pixel as non-promotable may be tracked using a pixel status array (PSA). Each PSA row may contain bits which correspond to the non-promotable status of pixels. Each row may include five pixels, the first four of which represent the pixels in a subspan. If the row corresponds to a valid subspan, a determination may be made as to whether any pixel in the subspan is represented by a one, indicating that the pixel is non-promotable. This row corresponds to a previous subspan that has been sent down rendering pipeline. If a one is present, then the current subspan may be stalled until the pixels of the previous subspan has gone through color calculation. If, in the row that has just been read, no pixels are represented by a one, then a determination may be made as to whether any pixels in the current subspan are non-promotable. If so, then the corresponding bit in the current PSA row may be set to one. Otherwise, the Z test may be performed on each pixel of the current subspan.
摘要翻译：在计算机图形渲染期间的Z测试以优化渲染的方式执行。可以使用像素状态阵列（PSA）跟踪不可升级的像素的状态。每个PSA行可以包含对应于像素的不可升级状态的位。每行可以包括五个像素，其中前四个表示子跨距中的像素。如果该行对应于有效的子跨度，则可以确定子跨越中的任何像素是否由一个表示，表示该像素是不可升级的。此行对应于已向下渲染管道发送的先前子跨。如果存在一个，那么当前的子跨越可能会停顿，直到前一个子跨越的像素经过颜色计算。如果在刚刚读取的行中没有像素由一个像素表示，则可以确定当前子跨距中的任何像素是否不可升级。如果是，则当前PSA行中的相应位可以被设置为1。否则，可以对当前子跨的每个像素执行Z测试。

6. 发明申请

US20070103487A1 PIXEL FILTERING USING SHARED FILTER RESOURCE BETWEEN OVERLAY AND TEXTURE MAPPING ENGINES 有权
标题翻译：使用过滤器和纹理映射引擎之间的共享过滤器资源进行像素过滤
公开(公告)号：US20070103487A1
公开(公告)日：2007-05-10
申请号：US11619124
申请日：2007-01-02
申请人： David Watson , Kim Meinerth , Indraneel Ghosh , Thomas Piazza , Val Cook
发明人： David Watson , Kim Meinerth , Indraneel Ghosh , Thomas Piazza , Val Cook
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G09G5/363 , G09G2340/125
摘要： A configurable filter module for providing shared filter resource between an overlay engine and a texture mapping engine of a graphics system. The configurable filter may comprise a plurality of linear blend units each of which receives data input from one of the overlay engine and a mapping engine cache, and generates a linear blend filter output respectively; and a filter output multiplexer which receives data output from the linear blend units and selects a proper byte ordering output, wherein the linear blend units serve as an overlay interpolator filter to perform linear blending of the data input from the overlay engine during a linear blend mode, and serve as a texture bilinear filter to perform bilinear filtering of the data input from the mapping engine cache during a bilinear filtering mode.
摘要翻译：一种可配置的过滤器模块，用于在叠加引擎和图形系统的纹理映射引擎之间提供共享过滤器资源。可配置滤波器可以包括多个线性混合单元，每个线性混合单元接收从叠加引擎之一和映射引擎高速缓存输入的数据，并分别产生线性混合滤波器输出; 以及滤波器输出多路复用器，其接收从线性混合单元输出的数据并选择适当的字节排序输出，其中线性混合单元用作叠加内插器滤波器，以在线性混合模式期间执行从覆盖引擎输入的数据的线性混合，并且用作纹理双线性滤波器以在双线性滤波模式期间对从映射引擎高速缓存输入的数据进行双线性滤波。

7. 发明申请

US20050289329A1 Conditional instruction for a single instruction, multiple data execution engine 审中-公开
标题翻译：单条指令的条件指令，多数据执行引擎
公开(公告)号：US20050289329A1
公开(公告)日：2005-12-29
申请号：US10879460
申请日：2004-06-29
申请人： Michael Dwyer , Hong Jiang , Thomas Piazza
发明人： Michael Dwyer , Hong Jiang , Thomas Piazza
IPC分类号： G06F9/38 , G06F15/00
CPC分类号： G06F9/3887 , G06F9/30036 , G06F9/30072 , G06F9/3885
摘要： According to some embodiments, a conditional Single Instruction, Multiple Data instruction is provided. For example, a first conditional instruction may be received at an n-channel SIMD execution engine. The first conditional instruction may be evaluated based on multiple channels of associated data, and the result of the evaluation may be stored in an n-bit conditional mask register. A second conditional instruction may then be received at the execution engine and the result may be copied from the conditional mask register to an n-bit wide, m-entry deep conditional stack.
摘要翻译：根据一些实施例，提供了条件单指令，多数据指令。例如，可以在n信道SIMD执行引擎处接收第一条件指令。可以基于相关数据的多个信道来评估第一条件指令，并且可以将评估结果存储在n位条件掩码寄存器中。然后可以在执行引擎处接收第二条件指令，并且可以将结果从条件屏蔽寄存器复制到n位宽的m入口深条件堆栈。

8. 发明申请

US20050155034A1 Processing architecture having passive threads and active semaphores 有权
标题翻译：具有被动线程和主动信号量的处理架构
公开(公告)号：US20050155034A1
公开(公告)日：2005-07-14
申请号：US10750583
申请日：2003-12-31
申请人： Hong Jiang , Thomas Piazza
发明人： Hong Jiang , Thomas Piazza
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/3009 , G06F9/3851 , G06F9/526
摘要： Multiple parallel passive threads of instructions coordinate access to shared resources using “active” semaphores. The semaphores are referred to as active because the semaphores send messages to execution and/or control circuitry to cause the state of a thread to change. A thread can be placed in an inactive state by a thread scheduler in response to an unresolved dependency, which can be indicated by a semaphore. A thread state variable corresponding to the dependency is used to indicate that the thread is in inactive mode. When the dependency is resolved a message is passed to control circuitry causing the dependency variable to be cleared. In response to the cleared dependency variable the thread is placed in an active state. Execution can proceed on the threads in the active state.
摘要翻译：指令的多个并行被动线程使用“活动”信号量协调对共享资源的访问。信号量被称为活动的，因为信号量向执行和/或控制电路发送消息以使得线程的状态改变。线程调度程序可以响应未解决的依赖关系将线程置于无效状态，这可以由信号量指示。与依赖关系对应的线程状态变量用于指示线程处于非活动模式。当依赖关系被解析时，消息被传递给控制电路，导致依赖变量被清除。响应于清除的依赖变量，线程处于活动状态。处于活动状态的线程可执行。

9. 发明申请

US20050149928A1 Behavioral model based multi-threaded architecture 失效
标题翻译：基于行为模型的多线程架构
公开(公告)号：US20050149928A1
公开(公告)日：2005-07-07
申请号：US10750090
申请日：2003-12-31
申请人： Hong Jiang , Thomas Piazza
发明人： Hong Jiang , Thomas Piazza
IPC分类号： G06F9/38 , G06F9/46 , G06F9/48
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/4843
摘要： Multiple parallel passive threads of instructions coordinate access to shared resources using “active” and “proactive” semaphores. The active semaphores send messages to execution and/or control circuitry to cause the state of a thread to change. A thread can be placed in an inactive state by a thread scheduler in response to an unresolved dependency, which can be indicated by a semaphore. A thread state variable corresponding to the dependency is used to indicate that the thread is in inactive mode. When the dependency is resolved a message is passed to control circuitry causing the dependency variable to be cleared. In response to the cleared dependency variable the thread is placed in an active state. Execution can proceed on the threads in the active state. A proactive semaphore operates in a similar manner except that the semaphore is configured by the thread dispatcher before or after the thread is dispatched to the execution circuitry for execution.
摘要翻译：指令的多个并行被动线程使用“主动”和“主动”信号量协调对共享资源的访问。主动信号量将消息发送到执行和/或控制电路，以使线程的状态发生变化。线程调度程序可以响应未解决的依赖关系将线程置于无效状态，这可以由信号量指示。与依赖关系对应的线程状态变量用于指示线程处于非活动模式。当依赖关系被解析时，消息被传递给控制电路，导致依赖变量被清除。响应于清除的依赖变量，线程处于活动状态。处于活动状态的线程可执行。主动信号量以类似的方式运行，除了信号量由线程分派器在线程发送到执行电路执行之前或之后配置。

10. 发明申请

US20050198644A1 Visual and graphical data processing using a multi-threaded architecture 有权
标题翻译：使用多线程架构的视觉和图形数据处理
公开(公告)号：US20050198644A1
公开(公告)日：2005-09-08
申请号：US10750589
申请日：2003-12-31
申请人： Hong Jiang , Thomas Piazza
发明人： Hong Jiang , Thomas Piazza
IPC分类号： G06F9/30 , G06F9/46
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087 , G06F9/52
摘要： Active and/or proactive semaphore mechanisms and thread synchronization techniques can be applied to various visual and graphical processing techniques.
摘要翻译：主动和/或主动信号量机制和线程同步技术可以应用于各种视觉和图形处理技术。

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