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1. 发明授权

US07594236B2 Thread to thread communication 有权
标题翻译：线程线程通信
公开(公告)号：US07594236B2
公开(公告)日：2009-09-22
申请号：US10880155
申请日：2004-06-28
申请人： Hong Jiang , Michael K. Dwyer
发明人： Hong Jiang , Michael K. Dwyer
IPC分类号： G06F3/00 , G06F15/16 , H04L9/32 , G06F13/00 , G06F7/04
CPC分类号： G06F9/542
摘要： Thread to thread communication is provided. A first thread registers with a gateway for receiving communication. Registration includes identifying a location for receiving messages. The gateway maps message payloads received from second threads to the location of the first thread. The first thread detects a payload in the location and consumes it for processing.
摘要翻译：提供线程到线程通信。第一个线程与网关注册以接收通信。注册包括识别用于接收消息的位置。网关将从第二线程接收的消息有效载荷映射到第一个线程的位置。第一个线程检测该位置中的有效载荷并将其用于处理。

2. 发明授权

US07219213B2 Flag bits evaluation for multiple vector SIMD channels execution 有权
标题翻译：多个矢量SIMD通道的标志位评估
公开(公告)号：US07219213B2
公开(公告)日：2007-05-15
申请号：US11015778
申请日：2004-12-17
申请人： Michael K. Dwyer , Hong Jiang
发明人： Michael K. Dwyer , Hong Jiang
IPC分类号： G06F15/80
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30101 , G06F9/3885 , G06F9/3887
摘要： According to some embodiments, a evaluation unit may be provided for Single Instruction, Multiple Data (SIMD) execution engine flag registers. For example, a horizontal evaluation unit might perform evaluation operations across multiple vectors being processed by the SIMD execution engine. According to some embodiments, a vertical evaluation unit might perform evaluation operations across multiple flag registers.
摘要翻译：根据一些实施例，可以为单指令，多数据（SIMD）执行引擎标志寄存器提供评估单元。例如，水平评估单元可以对由SIMD执行引擎处理的多个向量执行评估操作。根据一些实施例，垂直评估单元可以执行跨多个标志寄存器的评估操作。

3. 发明授权

US10297001B2 Reduced power implementation of computer instructions 有权
公开(公告)号：US10297001B2
公开(公告)日：2019-05-21
申请号：US14583300
申请日：2014-12-26
申请人： Subramaniam Maiyuran , Shubh B. Shah , Ashutosh Garg , Jin Xu , Thomas A. Piazza , Jorge F. Garcia Pabon , Michael K. Dwyer
发明人： Subramaniam Maiyuran , Shubh B. Shah , Ashutosh Garg , Jin Xu , Thomas A. Piazza , Jorge F. Garcia Pabon , Michael K. Dwyer
IPC分类号： G06T1/20 , G09G5/00 , G06T15/80 , G09G5/36 , G06F7/00 , G06F9/30
摘要： Systems and methods may provide a graphics processor that may identify operating conditions under which certain floating point instructions may utilize power to fewer hardware resources compared to when the instructions are executing under other operating conditions. The operating conditions may be determined by examining operands used in a given instruction, including the relative magnitudes of the operands and whether the operands may be taken as equal to certain defined values. The floating point instructions may include instructions for an addition operation, a multiplication operation, a compare operation, and/or a fused multiply-add operation.

4. 发明授权

US08279886B2 Dataport and methods thereof 有权
标题翻译：数据端口及其方法
公开(公告)号：US08279886B2
公开(公告)日：2012-10-02
申请号：US11024909
申请日：2004-12-30
申请人： Dinakar Munagala , Hong Jiang , Bishara Shomar , Val Cook , Michael K. Dwyer , Thomas Piazza
发明人： Dinakar Munagala , Hong Jiang , Bishara Shomar , Val Cook , Michael K. Dwyer , Thomas Piazza
IPC分类号： H04L12/28
CPC分类号： G06F13/1668
摘要： A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.
摘要翻译：无上下文（无状态）数据端口可能允许多个处理器对共享内存执行读写操作。操作可以包括例如诸如图像和视频操作的结构化数据操作。数据端口可以执行与块存储器操作相关联的寻址计算。因此，数据端口可能能够例如从其责任中减轻其服务的处理器。可以使用可以以标准和一般化方式实现的消息接口来访问数据端口，并且因此可以容易地在不同类型的处理器之间传送。

5. 发明申请

US20100031268A1 Thread ordering techniques 审中-公开
标题翻译：线程订购技术
公开(公告)号：US20100031268A1
公开(公告)日：2010-02-04
申请号：US12221083
申请日：2008-07-31
申请人： Michael K. Dwyer , Robert L. Farrell , Hong Jiang , Thomas A. Piazza
发明人： Michael K. Dwyer , Robert L. Farrell , Hong Jiang , Thomas A. Piazza
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Techniques are described that can be used to ensure ordered computation and/or retirement of threads in a multithreaded environment. Threads may contain bundled instances of work, each with unique ordering restrictions relative to other instances of work packaged in other threads in the system. When applied to 3D graphics, video and image processing domains allow unrestricted processing of threads until reaching their critical sections. Ordering may be required prior to executing critical sections and beyond.
摘要翻译：描述了可用于确保多线程环境中线程的有序计算和/或退出的技术。线程可能包含捆绑的工作实例，每个实例具有相对于系统中其他线程打包的其他工作实例的独特排序限制。当应用于3D图形时，视频和图像处理域允许不受限制地处理线程直到到达其关键部分。执行关键部分之前可能需要订购。

6. 发明申请

US20090006729A1 CACHE FOR A MULTI THREAD AND MULTI CORE SYSTEM AND METHODS THEREOF 有权
标题翻译：用于多线程和多核系统的缓存及其方法
公开(公告)号：US20090006729A1
公开(公告)日：2009-01-01
申请号：US11770120
申请日：2007-06-28
申请人： Thomas A. Piazza , Michael K. Dwyer , Scott Cheng
发明人： Thomas A. Piazza , Michael K. Dwyer , Scott Cheng
IPC分类号： G06F12/00
CPC分类号： G06F12/0859
摘要： According to one embodiment, the present disclosure generally provides a method for improving the performance of a cache of a processor. The method may include storing a plurality of data in a data Random Access Memory (RAM). The method may further include holding information for all outstanding requests forwarded to a next-level memory subsystem. The method may also include clearing information associated with a serviced request after the request has been fulfilled. The method may additionally include determining if a subsequent request matches an address supplied to one or more requests already in-flight to the next-level memory subsystem. The method may further include matching fulfilled requests serviced by the next-level memory subsystem to at least one requester who issued requests while an original request was in-flight to the next level memory subsystem. The method may also include storing information specific to each request, the information including a set attribute and a way attribute, the set and way attributes configured to identify where the returned data should be held in the data RAM once the data is returned, the information specific to each request further including at least one of thread ID, instruction queue position and color. The method may additionally include scheduling hit and miss data returns. Of course, various alternative embodiments are also within the scope of the present disclosure.
摘要翻译：根据一个实施例，本公开通常提供用于提高处理器的高速缓存的性能的方法。该方法可以包括将多个数据存储在数据随机存取存储器（RAM）中。该方法还可以包括保存转发到下一级存储器子系统的所有未完成请求的信息。该方法还可以包括在请求已经满足之后清除与服务请求相关联的信息。该方法可以另外包括确定后续请求是否匹配提供给已经在飞行中的一个或多个请求到下一级存储器子系统的地址。该方法还可以包括将下一级存储器子系统服务的满足的请求与在原始请求正在飞行到下一级存储器子系统时发出请求的至少一个请求者进行匹配。所述方法还可以包括存储特定于每个请求的信息，所述信息包括集合属性和方式属性，所述设置和方式属性被配置为在数据返回后识别返回的数据应保存在数据RAM中的位置，所述信息特定于每个请求还包括线程ID，指令队列位置和颜色中的至少一个。该方法可以另外包括调度命中和未命中数据返回。当然，各种替代实施例也在本公开的范围内。

7. 发明申请

US20110067035A1 Thread to Thread Communication 审中-公开
标题翻译：线程到线程通信
公开(公告)号：US20110067035A1
公开(公告)日：2011-03-17
申请号：US12947886
申请日：2010-11-17
申请人： Hong Jiang , Michael K. Dwyer
发明人： Hong Jiang , Michael K. Dwyer
IPC分类号： G06F9/46
CPC分类号： G06F9/542
摘要： Thread to thread communication is provided. A first thread registers with a gateway for receiving communication. Registration includes identifying a location for receiving messages. The gateway maps message payloads received from second threads to the location of the first thread. The first thread detects a payload in the location and consumes it for processing.
摘要翻译：提供线程到线程通信。第一个线程与网关注册以接收通信。注册包括识别用于接收消息的位置。网关将从第二线程接收的消息有效载荷映射到第一个线程的位置。第一个线程检测该位置中的有效载荷并将其用于处理。

8. 发明授权

US07526124B2 Match MSB digital image compression 有权
标题翻译：匹配MSB数字图像压缩
公开(公告)号：US07526124B2
公开(公告)日：2009-04-28
申请号：US11712046
申请日：2007-02-27
申请人： Michael K. Dwyer , Thomas A. Piazza
发明人： Michael K. Dwyer , Thomas A. Piazza
IPC分类号： G06K9/36 , G06K9/46 , G06K9/00
CPC分类号： H04N19/184 , H04N19/124 , H04N19/156 , H04N19/186 , H04N19/50
摘要： Methods, apparatus and computer readable medium are described that compress and/or decompress a digital image in a lossless or a lossy manner. In some embodiments, a display controller may compress a digital image by generating a symbol for each pel of the digital image. In particular, the symbol may represent a pel via a match vector and a channel error vector. The match vector may indicate which quantized channels of the pel matched quantized channels of a previous pel. Further, the channel error vector may comprise a lossless or lossy channel for each quantized channel of the pel that did not match a corresponding quantized channel of the previous pel. The channel error may also comprise a lossless or lossy channel error for each quantized channel of the pel that matched a corresponding quantized channel of the previous pel.
摘要翻译：描述了以无损或有损的方式对数字图像进行压缩和/或解压缩的方法，装置和计算机可读介质。在一些实施例中，显示控制器可以通过为数字图像的每个像素生成符号来压缩数字图像。特别地，符号可以经由匹配向量和信道误差向量来表示像素。匹配向量可以指示先前像素的像素匹配量化通道的哪个量化通道。此外，信道误差向量可以包括与先前像素的对应量化信道不匹配的像素的每个量化信道的无损或有损信道。信道误差还可以包括与先前像素的相应量化信道匹配的像素的每个量化信道的无损或有损信道误差。

9. 发明授权

US06369813B2 Processing polygon meshes using mesh pool window 失效
标题翻译：使用网格池窗口处理多边形网格
公开(公告)号：US06369813B2
公开(公告)日：2002-04-09
申请号：US09109257
申请日：1998-06-30
申请人： Vladimir Pentkovski , Deep Buch , Michael K. Dwyer , Hsien-Hsin Lee , Hsien-Cheng E. Hsieh
发明人： Vladimir Pentkovski , Deep Buch , Michael K. Dwyer , Hsien-Hsin Lee , Hsien-Cheng E. Hsieh
IPC分类号： G06T1500
CPC分类号： G06T17/20
摘要： The present invention is directed to a method and apparatus for processing normalized meshes. The normalized meshes are formed by N polygons which have M vertices. M vertex coordinates are stored in a vertex array corresponding to the M vertices of the N polygons. N polygon indices are stored in an index array. Each of the N polygon indices references a predetermined number of the M vertex coordinates. A first subset of the index array having N1 polygon indices is determined. A second subset of the vertex array is selected such that the second subset contains M1 vertex coordinates corresponding entirely to the N1 polygon indices in the first subset. The second subset defines a window having a small size relative to the vertex array. The M1 vertex coordinates in the second subset are processed to generate processed data. The processed data are then concurrently sent to a graphics processor in an on-line manner.
摘要翻译：本发明涉及一种用于处理归一化网格的方法和装置。归一化网格由具有M个顶点的N个多边形形成。 M顶点坐标存储在与N个多边形的M个顶点对应的顶点数组中。 N个多边形索引存储在索引数组中。 N个多边形索引中的每一个引用预定数量的M个顶点坐标。确定具有N1个多边形索引的索引阵列的第一子集。选择顶点阵列的第二子集，使得第二子集包含完全对应于第一子集中的N1多边形索引的M1顶点坐标。第二个子集定义相对于顶点数组具有小尺寸的窗口。处理第二个子集中的M1顶点坐标以产生处理后的数据。然后，处理的数据以在线方式同时发送到图形处理器。

10. 发明申请

US20130038616A1 Dataport and Methods Thereof 有权
标题翻译：数据端口及其方法
公开(公告)号：US20130038616A1
公开(公告)日：2013-02-14
申请号：US13625041
申请日：2012-09-24
申请人： Dinakar MUNAGALA , Hong JIANG , Bishara SHOMAR , Val COOK , Michael K. DWYER , Thomas PIAZZA
发明人： Dinakar MUNAGALA , Hong JIANG , Bishara SHOMAR , Val COOK , Michael K. DWYER , Thomas PIAZZA
IPC分类号： G06F15/80
CPC分类号： G06F13/1668
摘要： A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.
摘要翻译：无上下文（无状态）数据端口可能允许多个处理器对共享内存执行读写操作。操作可以包括例如诸如图像和视频操作的结构化数据操作。数据端口可以执行与块存储器操作相关联的寻址计算。因此，数据端口可能能够例如从其责任中减轻其服务的处理器。可以使用可以以标准和一般化方式实现的消息接口来访问数据端口，并且因此可以容易地在不同类型的处理器之间传送。

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