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1. 发明授权

US09875931B2 Semiconductor device having interconnection structure 有权
公开(公告)号：US09875931B2
公开(公告)日：2018-01-23
申请号：US15201922
申请日：2016-07-05
申请人： Dohyun Lee , Youngwoo Park , Junghoon Park , Jaeduk Lee
发明人： Dohyun Lee , Youngwoo Park , Junghoon Park , Jaeduk Lee
IPC分类号： H01L21/00 , H01L21/768 , H01L27/1157 , H01L27/11582 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/76816 , H01L23/522 , H01L23/5226 , H01L23/5283 , H01L23/53266 , H01L23/53295 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

2. 发明授权

US10418278B2 Semiconductor device having interconnection structure 有权
公开(公告)号：US10418278B2
公开(公告)日：2019-09-17
申请号：US15857961
申请日：2017-12-29
申请人： Dohyun Lee , Youngwoo Park , Junghoon Park , Jaeduk Lee
发明人： Dohyun Lee , Youngwoo Park , Junghoon Park , Jaeduk Lee
IPC分类号： H01L21/00 , H01L21/768 , H01L27/1157 , H01L27/11582 , H01L23/522 , H01L23/532 , H01L27/11573 , H01L27/11575 , H01L23/528
摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

3. 发明授权

US09299707B2 Three-dimensional semiconductor devices with current path selection structure 有权
标题翻译：具有电流路径选择结构的三维半导体器件
公开(公告)号：US09299707B2
公开(公告)日：2016-03-29
申请号：US14150452
申请日：2014-01-08
申请人： Jaeduk Lee , Youngwoo Park , Jintaek Park , Dohyun Lee , Kohji Kanamori
发明人： Jaeduk Lee , Youngwoo Park , Jintaek Park , Dohyun Lee , Kohji Kanamori
IPC分类号： H01L27/108 , H01L27/105 , H01L27/115 , G11C16/10 , G11C16/14
CPC分类号： H01L27/1052 , G11C16/10 , G11C16/14 , H01L27/11524 , H01L27/11556
摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.
摘要翻译：提供三维半导体器件及其操作方法。三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。

4. 发明申请

US20160005760A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20160005760A1
公开(公告)日：2016-01-07
申请号：US14725476
申请日：2015-05-29
申请人： Dohyun Lee , Jaegoo Lee , Young-Jin Kwon , Youngwoo Park , Jaeduk Lee
发明人： Dohyun Lee , Jaegoo Lee , Young-Jin Kwon , Youngwoo Park , Jaeduk Lee
IPC分类号： H01L27/115 , H01L29/10 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/1033 , H01L29/7926
摘要： A semiconductor device includes a lower stack structure including lower gate electrodes and lower insulating layers that are alternately and repeatedly stacked on a substrate. The semiconductor device includes an upper stack structure including upper gate electrodes and upper insulating layers that are alternately and repeatedly stacked on the lower stack structure. A lower channel structure penetrates the lower stack structure. An upper channel structure penetrates and is connected to the upper stack structure. A lower vertical insulator is disposed between the lower stack structure and the lower channel structure. The lower channel structure includes a first vertical semiconductor pattern connected to the substrate, and a first connecting semiconductor pattern disposed on the first vertical semiconductor pattern. The upper channel structure includes a second vertical semiconductor pattern electrically connected to the first vertical semiconductor pattern with the first connecting semiconductor pattern disposed therebetween.
摘要翻译：半导体器件包括下层堆叠结构，其包括交替重复堆叠在衬底上的下栅电极和下绝缘层。半导体器件包括上堆叠结构，其包括交替重复堆叠在下堆叠结构上的上栅电极和上绝缘层。下部通道结构穿透下部堆叠结构。上通道结构穿透并连接到上堆叠结构。下部垂直绝缘体设置在下部堆叠结构和下部通道结构之间。下通道结构包括连接到基板的第一垂直半导体图案和布置在第一垂直半导体图案上的第一连接半导体图案。上通道结构包括电连接到第一垂直半导体图案的第二垂直半导体图案，其间设置有第一连接半导体图案。

5. 发明申请

US20140197469A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICES WITH CURRENT PATH SELECTION STRUCTURE AND METHODS OF OPERATING THE SAME 有权
标题翻译：具有电流路径选择结构的三维半导体器件及其操作方法
公开(公告)号：US20140197469A1
公开(公告)日：2014-07-17
申请号：US14150452
申请日：2014-01-08
申请人： Jaeduk Lee , Youngwoo Park , Jintaek Park , Dohyun Lee , Kohji Kanamori
发明人： Jaeduk Lee , Youngwoo Park , Jintaek Park , Dohyun Lee , Kohji Kanamori
IPC分类号： H01L27/105
CPC分类号： H01L27/1052 , G11C16/10 , G11C16/14 , H01L27/11524 , H01L27/11556
摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.
摘要翻译：提供三维半导体器件及其操作方法。三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。

6. 发明申请

US20110169068A1 NON-VOLATILE MEMORY DEVICES HAVING A FLOATING GATE CAP BETWEEN A FLOATING GATE AND A GATE INSULATING LAYER 有权
标题翻译：具有浮动门和门绝缘层之间的浮动门盖的非易失性存储器件
公开(公告)号：US20110169068A1
公开(公告)日：2011-07-14
申请号：US12986553
申请日：2011-01-07
申请人： JAEDUK LEE , Albert Fayrushin , ByungKyu Cho , Jungdal Choi , Sunghoi Hur , Kwang Soo Seol , Dohyun Lee
发明人： JAEDUK LEE , Albert Fayrushin , ByungKyu Cho , Jungdal Choi , Sunghoi Hur , Kwang Soo Seol , Dohyun Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L27/11521 , H01L29/42324 , H01L29/4234 , H01L29/42352 , H01L29/7881 , H01L29/792
摘要： Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.
摘要翻译：提供了非易失性存储器件及其形成方法。隧道绝缘图案设置在基板上，并且浮动栅极设置在隧道绝缘图案上。在浮置栅极上设置具有电荷陷阱位置的浮动栅极盖，并且在浮动栅极盖上设置栅极电介质图案。控制栅极设置在栅极电介质图案上。

7. 发明授权

US08791520B2 Non-volatile memory devices having a floating gate cap between a floating gate and a gate insulating layer 有权
标题翻译：在浮置栅极和栅极绝缘层之间具有浮动栅极盖的非易失性存储器件
公开(公告)号：US08791520B2
公开(公告)日：2014-07-29
申请号：US12986553
申请日：2011-01-07
申请人： Jaeduk Lee , Albert Fayrushin , ByungKyu Cho , Jungdal Choi , Sunghoi Hur , Kwang Soo Seol , Dohyun Lee
发明人： Jaeduk Lee , Albert Fayrushin , ByungKyu Cho , Jungdal Choi , Sunghoi Hur , Kwang Soo Seol , Dohyun Lee
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/42336 , H01L27/11521 , H01L29/42324 , H01L29/4234 , H01L29/42352 , H01L29/7881 , H01L29/792
摘要： Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.
摘要翻译：提供了非易失性存储器件及其形成方法。隧道绝缘图案设置在基板上，并且浮动栅极设置在隧道绝缘图案上。在浮置栅极上设置具有电荷陷阱位置的浮动栅极盖，并且在浮动栅极盖上设置栅极电介质图案。控制栅极设置在栅极电介质图案上。

8. 发明授权

US08129049B2 Jelly-roll having active material layer with different loading amount 有权
标题翻译：果冻卷具有不同负载量的活性物质层
公开(公告)号：US08129049B2
公开(公告)日：2012-03-06
申请号：US12532687
申请日：2008-03-24
申请人： Jong Hee Kim , Dongmyung Kim , Hyungook Yoon , Yong Jeong Kim , Joo-Hwan Sung , Seung W. Chu , Sung-Pil Yoon , Dohyun Lee
发明人： Jong Hee Kim , Dongmyung Kim , Hyungook Yoon , Yong Jeong Kim , Joo-Hwan Sung , Seung W. Chu , Sung-Pil Yoon , Dohyun Lee
IPC分类号： H01M4/00 , H01M4/13 , H01M6/48 , H01M10/18
CPC分类号： H01M10/0431 , H01M10/0587
摘要： Disclosed herein is a jelly-roll type electrode assembly (“jelly-roll”) of a cathode/separator/anode structure, wherein the jelly-roll is constructed in a structure in which each electrode has active material layers formed on opposite major surfaces of a sheet-type current collector, the loading amount of an active material for the inner active material layer, constituting the inner surface of each sheet when each sheet is wound, is less than that of an active material for the outer active material layer, constituting the outer surface of each sheet when each sheet is wound, and the loading amount of the active material for the inner active material layer gradually increases from the central region of each wound sheet to the outermost region of each wound sheet.
摘要翻译：本文公开了阴极/分离器/阳极结构的胶卷式电极组件（“胶卷”），其中胶卷被构造成其中每个电极具有形成在相对主表面上的活性材料层的结构构成片材每个片材的内表面的构成内部活性物质层的活性物质的负载量小于外部活性物质层的活性物质的负载量，构成每个片材被卷绕时的每个片材的外表面，并且用于内部活性材料层的活性材料的负载量从每个缠绕片材的中心区域逐渐增加到每个缠绕片材的最外部区域。

9. 发明申请

US20100104930A1 JELLY-ROLL HAVING ACTIVE MATERIAL LAYER WITH DIFFERENT LOADING AMOUNT 有权
标题翻译：具有不同负载量的活性材料层的JELLY-ROLL
公开(公告)号：US20100104930A1
公开(公告)日：2010-04-29
申请号：US12532687
申请日：2008-03-24
申请人： Jong Hee Kim , Dongmyung Kim , Hyungook Yoon , Yong Jeong Kim , Joo-Hwan Sung , Seung W. Chu , Sung-Pil Yoon , Dohyun Lee
发明人： Jong Hee Kim , Dongmyung Kim , Hyungook Yoon , Yong Jeong Kim , Joo-Hwan Sung , Seung W. Chu , Sung-Pil Yoon , Dohyun Lee
IPC分类号： H01M6/10
CPC分类号： H01M10/0431 , H01M10/0587
摘要： Disclosed herein is a jelly-roll type electrode assembly (“jelly-roll”) of a cathode/separator/anode structure, wherein the jelly-roll is constructed in a structure in which each electrode has active material layers formed on opposite major surfaces of a sheet-type current collector, the loading amount of an active material for the inner active material layer, constituting the inner surface of each sheet when each sheet is wound, is less than that of an active material for the outer active material layer, constituting the outer surface of each sheet when each sheet is wound, and the loading amount of the active material for the inner active material layer gradually increases from the central region of each wound sheet to the outermost region of each wound sheet.
摘要翻译：本文公开了阴极/分离器/阳极结构的胶卷式电极组件（“胶卷”），其中胶卷被构造成其中每个电极具有形成在相对主表面上的活性材料层的结构构成片材每个片材的内表面的构成内部活性物质层的活性物质的负载量小于外部活性物质层的活性物质的负载量，构成每个片材被卷绕时的每个片材的外表面，并且用于内部活性材料层的活性材料的负载量从每个缠绕片材的中心区域逐渐增加到每个缠绕片材的最外部区域。

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