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1. 发明申请

US20150333059A1 SEMICONDUCTOR DEVICES INCLUDING ISOLATION GATE LINES BETWEEN ACTIVE PATTERNS AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件，包括活性图案之间的隔离栅格线及其制造方法
公开(公告)号：US20150333059A1
公开(公告)日：2015-11-19
申请号：US14642069
申请日：2015-03-09
申请人： Dongbok Lee , KiVin Im , Youngsoo Lim , SoonMok Ha , Sung-Wook Hwang , Mansug Kang , Inseak Hwang
发明人： Dongbok Lee , KiVin Im , Youngsoo Lim , SoonMok Ha , Sung-Wook Hwang , Mansug Kang , Inseak Hwang
IPC分类号： H01L27/088 , H01L27/105
CPC分类号： H01L27/10891 , H01L27/088 , H01L27/1052 , H01L27/10814 , H01L27/10876
摘要： A semiconductor memory device includes a substrate having active regions extending in a first direction and separated therealong by a device isolation layer, and conductive word lines extending on the substrate in a second direction intersecting the first direction. Ones of the word lines extending between the active regions define isolation gate lines, which are insulated from the active regions by the device isolation layer. Edges of the active regions adjacent the isolation gate lines respectively include first and second corners that are spaced apart from an adjacent one of the isolation gate lines by substantially equal distances. Related fabrication methods are also discussed.
摘要翻译：半导体存储器件包括具有在第一方向上延伸并且由器件隔离层分离的有源区的衬底，以及在与第一方向相交的第二方向上在衬底上延伸的导电字线。在有源区域之间延伸的字线的一部分限定了通过器件隔离层与有源区域绝缘的隔离栅极线。邻近隔离栅极线的有源区的边缘分别包括通过基本上相等的距离与相邻隔离栅极线间隔开的第一和第二拐角。还讨论了相关的制造方法。

2. 发明授权

US09627202B2 Methods for forming fine patterns of semiconductor device 有权
公开(公告)号：US09627202B2
公开(公告)日：2017-04-18
申请号：US14822438
申请日：2015-08-10
申请人： SoonMok Ha , Sung-Wook Hwang , Joonsoo Park , Dae-Yong Kang , Byungjun Jeon
发明人： SoonMok Ha , Sung-Wook Hwang , Joonsoo Park , Dae-Yong Kang , Byungjun Jeon
IPC分类号： H01L21/027 , H01L21/033
CPC分类号： H01L21/0271 , H01L21/0334 , H01L21/0337 , H01L21/0338
摘要： The inventive concept provides methods for forming fine patterns of a semiconductor device. The method includes forming a buffer mask layer having first holes on a hard mask layer including a first region and a second region around the first region, forming first pillars filling the first holes and disposed on the buffer mask layer in the first region and second pillars disposed on the buffer mask layer in the second region, forming a block copolymer layer covering the first and second pillars on the buffer mask layer, phase-separating the block copolymer layer to form first block patterns spaced apart from the first and second pillars and a second block pattern surrounding the first and second pillars and the first block patterns, removing the first block patterns, and forming second holes in the buffer mask layer under the first block patterns.

3. 发明申请

US20160042965A1 METHODS FOR FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件精细图案的方法
公开(公告)号：US20160042965A1
公开(公告)日：2016-02-11
申请号：US14822438
申请日：2015-08-10
申请人： SoonMok Ha , Sung-Wook Hwang , Joonsoo Park , Dae-Yong Kang , Byungjun Jeon
发明人： SoonMok Ha , Sung-Wook Hwang , Joonsoo Park , Dae-Yong Kang , Byungjun Jeon
IPC分类号： H01L21/308
CPC分类号： H01L21/0271 , H01L21/0334 , H01L21/0337 , H01L21/0338
摘要： The inventive concept provides methods for forming fine patterns of a semiconductor device. The method includes forming a buffer mask layer having first holes on a hard mask layer including a first region and a second region around the first region, forming first pillars filling the first holes and disposed on the buffer mask layer in the first region and second pillars disposed on the buffer mask layer in the second region, forming a block copolymer layer covering the first and second pillars on the buffer mask layer, phase-separating the block copolymer layer to form first block patterns spaced apart from the first and second pillars and a second block pattern surrounding the first and second pillars and the first block patterns, removing the first block patterns, and forming second holes in the buffer mask layer under the first block patterns.
摘要翻译：本发明构思提供了形成半导体器件精细图案的方法。该方法包括在包括第一区域的硬掩模层和在第一区域周围的第二区域的硬掩模层上形成具有第一孔的缓冲掩模层，形成填充第一孔的第一柱并且设置在第一区域中的缓冲掩模层上，设置在第二区域中的缓冲掩模层上，形成覆盖缓冲掩模层上的第一和第二柱的嵌段共聚物层，相分离嵌段共聚物层以形成与第一和第二柱间隔开的第一嵌段图案和围绕第一和第二柱和第一块图案的第二块图案，去除第一块图案，以及在第一块图案之下在缓冲掩模层中形成第二孔。

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