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1. 发明申请

US20150333059A1 SEMICONDUCTOR DEVICES INCLUDING ISOLATION GATE LINES BETWEEN ACTIVE PATTERNS AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件，包括活性图案之间的隔离栅格线及其制造方法
公开(公告)号：US20150333059A1
公开(公告)日：2015-11-19
申请号：US14642069
申请日：2015-03-09
申请人： Dongbok Lee , KiVin Im , Youngsoo Lim , SoonMok Ha , Sung-Wook Hwang , Mansug Kang , Inseak Hwang
发明人： Dongbok Lee , KiVin Im , Youngsoo Lim , SoonMok Ha , Sung-Wook Hwang , Mansug Kang , Inseak Hwang
IPC分类号： H01L27/088 , H01L27/105
CPC分类号： H01L27/10891 , H01L27/088 , H01L27/1052 , H01L27/10814 , H01L27/10876
摘要： A semiconductor memory device includes a substrate having active regions extending in a first direction and separated therealong by a device isolation layer, and conductive word lines extending on the substrate in a second direction intersecting the first direction. Ones of the word lines extending between the active regions define isolation gate lines, which are insulated from the active regions by the device isolation layer. Edges of the active regions adjacent the isolation gate lines respectively include first and second corners that are spaced apart from an adjacent one of the isolation gate lines by substantially equal distances. Related fabrication methods are also discussed.
摘要翻译：半导体存储器件包括具有在第一方向上延伸并且由器件隔离层分离的有源区的衬底，以及在与第一方向相交的第二方向上在衬底上延伸的导电字线。在有源区域之间延伸的字线的一部分限定了通过器件隔离层与有源区域绝缘的隔离栅极线。邻近隔离栅极线的有源区的边缘分别包括通过基本上相等的距离与相邻隔离栅极线间隔开的第一和第二拐角。还讨论了相关的制造方法。

2. 发明授权

US09627202B2 Methods for forming fine patterns of semiconductor device 有权
公开(公告)号：US09627202B2
公开(公告)日：2017-04-18
申请号：US14822438
申请日：2015-08-10
申请人： SoonMok Ha , Sung-Wook Hwang , Joonsoo Park , Dae-Yong Kang , Byungjun Jeon
发明人： SoonMok Ha , Sung-Wook Hwang , Joonsoo Park , Dae-Yong Kang , Byungjun Jeon
IPC分类号： H01L21/027 , H01L21/033
CPC分类号： H01L21/0271 , H01L21/0334 , H01L21/0337 , H01L21/0338
摘要： The inventive concept provides methods for forming fine patterns of a semiconductor device. The method includes forming a buffer mask layer having first holes on a hard mask layer including a first region and a second region around the first region, forming first pillars filling the first holes and disposed on the buffer mask layer in the first region and second pillars disposed on the buffer mask layer in the second region, forming a block copolymer layer covering the first and second pillars on the buffer mask layer, phase-separating the block copolymer layer to form first block patterns spaced apart from the first and second pillars and a second block pattern surrounding the first and second pillars and the first block patterns, removing the first block patterns, and forming second holes in the buffer mask layer under the first block patterns.

3. 发明申请

US20160042965A1 METHODS FOR FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件精细图案的方法
公开(公告)号：US20160042965A1
公开(公告)日：2016-02-11
申请号：US14822438
申请日：2015-08-10
申请人： SoonMok Ha , Sung-Wook Hwang , Joonsoo Park , Dae-Yong Kang , Byungjun Jeon
发明人： SoonMok Ha , Sung-Wook Hwang , Joonsoo Park , Dae-Yong Kang , Byungjun Jeon
IPC分类号： H01L21/308
CPC分类号： H01L21/0271 , H01L21/0334 , H01L21/0337 , H01L21/0338
摘要： The inventive concept provides methods for forming fine patterns of a semiconductor device. The method includes forming a buffer mask layer having first holes on a hard mask layer including a first region and a second region around the first region, forming first pillars filling the first holes and disposed on the buffer mask layer in the first region and second pillars disposed on the buffer mask layer in the second region, forming a block copolymer layer covering the first and second pillars on the buffer mask layer, phase-separating the block copolymer layer to form first block patterns spaced apart from the first and second pillars and a second block pattern surrounding the first and second pillars and the first block patterns, removing the first block patterns, and forming second holes in the buffer mask layer under the first block patterns.
摘要翻译：本发明构思提供了形成半导体器件精细图案的方法。该方法包括在包括第一区域的硬掩模层和在第一区域周围的第二区域的硬掩模层上形成具有第一孔的缓冲掩模层，形成填充第一孔的第一柱并且设置在第一区域中的缓冲掩模层上，设置在第二区域中的缓冲掩模层上，形成覆盖缓冲掩模层上的第一和第二柱的嵌段共聚物层，相分离嵌段共聚物层以形成与第一和第二柱间隔开的第一嵌段图案和围绕第一和第二柱和第一块图案的第二块图案，去除第一块图案，以及在第一块图案之下在缓冲掩模层中形成第二孔。

4. 发明申请

US20100136745A1 POP PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译： POP包装及其制造方法
公开(公告)号：US20100136745A1
公开(公告)日：2010-06-03
申请号：US12698352
申请日：2010-02-02
申请人： Sung-Wook Hwang
发明人： Sung-Wook Hwang
IPC分类号： H01L21/60 , H01L21/50
CPC分类号： H05K1/181 , H01L23/49811 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2225/06568 , H01L2225/1023 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H05K3/3421 , H05K3/3447 , H05K2201/10515 , H05K2201/10689 , H05K2201/10704 , H05K2201/10734 , H05K2201/10946 , Y02P70/611 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of fabricating a package-on-package (POP) package is disclosed. The method includes preparing a first semiconductor package including a first substrate having external contact electrodes and a first semiconductor chip mounted on the first substrate, and preparing a second semiconductor package including a second substrate having external contact electrodes and a second semiconductor chip mounted on the second substrate. The method further includes forming lead lines in the second semiconductor package, the lead lines being electrically connected to the external contact electrodes of the second substrate, and stacking the second semiconductor package on the first semiconductor package and electrically connecting the external contact electrodes of the first substrate to the external contact electrodes of the second substrate using the lead lines.
摘要翻译：公开了一种制造封装封装（POP）封装的方法。该方法包括制备包括具有外部接触电极的第一基板和安装在第一基板上的第一半导体芯片的第一半导体封装，以及制备包括具有外部接触电极的第二基板和安装在第二基板上的第二半导体芯片的第二半导体封装基质。该方法还包括在第二半导体封装中形成引线，引线与第二衬底的外部接触电极电连接，并将第二半导体封装堆叠在第一半导体封装上，并电连接第一半导体封装的外部接触电极使用引线将衬底施加到第二衬底的外部接触电极。

5. 发明授权

US07723834B2 POP package and method of fabricating the same 有权
标题翻译： POP包装及其制造方法
公开(公告)号：US07723834B2
公开(公告)日：2010-05-25
申请号：US11851284
申请日：2007-09-06
申请人： Sung-Wook Hwang
发明人： Sung-Wook Hwang
IPC分类号： H01L23/495
CPC分类号： H05K1/181 , H01L23/49811 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2225/06568 , H01L2225/1023 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H05K3/3421 , H05K3/3447 , H05K2201/10515 , H05K2201/10689 , H05K2201/10704 , H05K2201/10734 , H05K2201/10946 , Y02P70/611 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A package-on-package (POP) package in which semiconductor packages are stacked using lead lines rather than conventional solder balls, and a fabricating method thereof are provided. According to the POP package and the fabricating method thereof of the present invention, the POP package is prevented from being short-circuited even when an underlying semiconductor package gets thicker and the POP package can sufficiently withstand deformation caused by post-fabrication warpage.
摘要翻译：一种封装封装（POP）封装，其中使用引线而不是常规焊球堆叠半导体封装，并提供其制造方法。根据本发明的POP封装及其制造方法，即使下面的半导体封装变厚并且POP封装能够充分地承受由后制造翘曲引起的变形，也可以防止POP封装短路。

6. 发明授权

US07385183B2 Substrate processing apparatus using neutralized beam and method thereof 有权
标题翻译：使用中和束的基板处理装置及其方法
公开(公告)号：US07385183B2
公开(公告)日：2008-06-10
申请号：US11335725
申请日：2006-01-19
申请人： Sung-Chan Park , Sung-Wook Hwang
发明人： Sung-Chan Park , Sung-Wook Hwang
IPC分类号： H05H3/02 , H01J37/26 , H01S1/00
CPC分类号： H01J37/026 , H01J37/32357 , H01J2237/0042 , H01J2237/334
摘要： In a substrate processing apparatus using a neutralized beam and a method thereof, the substrate processing apparatus includes: an ion source for emitting an ion beam at an emitting angle; reflectors at which the ion beam emitted by the ion source is incident and subject to 2n collisions (where n is a positive integer) in first and second opposite directions to neutralize the ion beam as a neutralized beam and to restore a direction of propagation of the neutralized beam to the emitting angle of the ion beam; and a substrate at which the neutralized beam generated by the reflectors is incident on to perform a process. Accordingly, an incident angle of the resultant neutralized beam is perpendicular to a substrate, while the direction of propagation of the originating ion source and the surface of the substrate are maintained to be perpendicular to each other.
摘要翻译：在使用中和束的基板处理装置及其方法中，基板处理装置包括：用于以发射角发射离子束的离子源; 由离子源发射的离子束入射并且在第一和第二相反方向上经受2n次碰撞（其中n是正整数）的反射器，以将离子束中和作为中和的光束，并恢复所述离子束的传播方向中和的束到离子束的发射角; 以及由反射器产生的被中和的光束入射的基板，以执行处理。因此，所得中和束的入射角垂直于基板，而原始离子源和基板的表面的传播方向保持彼此垂直。

7. 发明申请

US20070181820A1 Apparatus and method for controlling ion beam 有权
标题翻译：用于控制离子束的装置和方法
公开(公告)号：US20070181820A1
公开(公告)日：2007-08-09
申请号：US11703130
申请日：2007-02-07
申请人： Sung-Wook Hwang , Do-Haing Lee , Chul-Ho Shin , Jong-Woo Sun
发明人： Sung-Wook Hwang , Do-Haing Lee , Chul-Ho Shin , Jong-Woo Sun
IPC分类号： H01J3/14
CPC分类号： H01J37/08 , H01J27/024 , H01J2237/061 , H01J2237/3151 , H01J2237/31701
摘要： An apparatus and/or method for controlling an ion beam may be provided, and/or a method for preparing an extraction electrode for the same may be provided. In the apparatus, a plurality of extraction electrodes may be disposed in a path of an ion beam. At least one extraction electrode may include a plurality of sub-grids.
摘要翻译：可以提供用于控制离子束的装置和/或方法，和/或可以提供用于制备其的提取电极的方法。在该装置中，多个提取电极可以设置在离子束的路径中。至少一个提取电极可以包括多个子网格。

8. 发明申请

US20060196425A1 Reflectors, substrate processing apparatuses and methods for the same 审中-公开
标题翻译：反射器，基板处理装置及其方法
公开(公告)号：US20060196425A1
公开(公告)日：2006-09-07
申请号：US11350795
申请日：2006-02-10
申请人： Sung-Wook Hwang , Chul-Ho Shin
发明人： Sung-Wook Hwang , Chul-Ho Shin
IPC分类号： C23C16/00 , B32B13/04 , B32B9/00 , C23F1/00 , H01L21/306 , B32B15/04 , H05H1/24 , B32B19/00
CPC分类号： H01J37/32633 , C23F4/00 , H01J37/32357
摘要： A substrate processing apparatus may include a processing chamber including a plasma generating unit arranged in an upper region thereof. A grid system, which may extract ions from plasma formed by the plasma generating unit and may accelerate the ions to have substantially uniform directivity. The grid system may be positioned below the plasma generating unit. A reflector may be arranged below the grid system and may include parallel reflecting plates for converting the ions accelerated from the grid system into neutral beams.
摘要翻译：基板处理装置可以包括处理室，其包括布置在其上部区域中的等离子体产生单元。栅格系统，其可以从由等离子体发生单元形成的等离子体提取离子，并且可以加速离子以具有基本均匀的方向性。栅格系统可以位于等离子体生成单元的下方。反射器可以布置在栅格系统下方，并且可以包括用于将从栅格系统加速的离子转换成中性光束的平行反射板。

9. 发明申请

US20060163466A1 Substrate processing apparatus using neutralized beam and method thereof 有权
标题翻译：使用中和束的基板处理装置及其方法
公开(公告)号：US20060163466A1
公开(公告)日：2006-07-27
申请号：US11335725
申请日：2006-01-19
申请人： Sung-Chan Park , Sung-Wook Hwang
发明人： Sung-Chan Park , Sung-Wook Hwang
IPC分类号： H05H3/02
CPC分类号： H01J37/026 , H01J37/32357 , H01J2237/0042 , H01J2237/334
摘要： In a substrate processing apparatus using a neutralized beam and a method thereof, the substrate processing apparatus includes: an ion source for emitting an ion beam at an emitting angle; reflectors at which the ion beam emitted by the ion source is incident and subject to 2n collisions (where n is a positive integer) in first and second opposite directions to neutralize the ion beam as a neutralized beam and to restore a direction of propagation of the neutralized beam to the emitting angle of the ion beam; and a substrate at which the neutralized beam generated by the reflectors is incident on to perform a process. Accordingly, an incident angle of the resultant neutralized beam is perpendicular to a substrate, while the direction of propagation of the originating ion source and the surface of the substrate are maintained to be perpendicular to each other.
摘要翻译：在使用中和束的基板处理装置及其方法中，基板处理装置包括：用于以发射角发射离子束的离子源; 由离子源发射的离子束入射并在第一和第二相反方向经受2n次碰撞（其中n是正整数）的反射器，以将离子束中和作为中和束并且恢复其中的传播方向中和的束到离子束的发射角; 以及由反射器产生的被中和的光束入射的基板，以执行处理。因此，所得中和束的入射角垂直于基板，而原始离子源和基板的表面的传播方向保持彼此垂直。

10. 发明申请

US20050275042A1 Semiconductor device including a field effect transistor and method of forming thereof 失效
标题翻译：包括场效应晶体管的半导体器件及其形成方法
公开(公告)号：US20050275042A1
公开(公告)日：2005-12-15
申请号：US11138034
申请日：2005-05-26
申请人： Sung-Wook Hwang , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
发明人： Sung-Wook Hwang , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
IPC分类号： H01L29/78 , H01L21/336 , H01L29/49 , H01L29/51 , H01L29/74
CPC分类号： H01L29/4236 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66553 , H01L29/66621
摘要： A semiconductor device including a transistor and a method of forming thereof are provided. The semiconductor device comprises a metal gate electrode. A lower portion of the metal gate electrode fills a channel trench formed at a predetermined region of a substrate, and an upper portion of the metal gate electrode protrudes on the substrate. A gate insulating layer is interposed between inner sidewalls and a bottom surface of the channel trench, and the metal gate electrode. Source/drain regions are formed at the substrate in both sides of the metal gate electrode.
摘要翻译：提供了包括晶体管及其形成方法的半导体器件。半导体器件包括金属栅电极。金属栅电极的下部填充形成在衬底的预定区域处的沟道沟槽，并且金属栅电极的上部在衬底上突出。栅极绝缘层插入在沟道沟槽的内侧壁和底表面之间以及金属栅电极之间。源极/漏极区域形成在金属栅电极两侧的衬底处。

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