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1. 发明申请

US20230116607A1 INTEGRATED CIRCUIT PROTECTIONS AGAINST REMOVAL AND ORACLE-GUIDED ATTACKS 有权
公开(公告)号：US20230116607A1
公开(公告)日：2023-04-13
申请号：US17496055
申请日：2021-10-07
申请人： Duke University
发明人： Jonti Talukdar , Krishnendu Chakrabarty
IPC分类号： G06F21/75 , G11C29/36
摘要： An integrated circuit (IC) protection circuit for an IC includes a controller with a barrier finite state machine (FSM) having a key sequence input that unlocks the controller; and a signal scrambler coupled to receive at least two initialization inputs and a primary input path and output a signal to the IC, wherein at least one initialization input of the at least two initialization inputs is based on an output of the barrier FSM. The IC protection circuit can further include a dynamic authentication circuit coupled to receive the output of the barrier finite state machine and output a signal to the signal scrambler for one of the at least two initialization inputs. The dynamic authentication circuit can be formed of a dynamic sequence generator and a dynamic sequence authenticator, each formed of one or more reconfigurable linear feedback shift registers, and a comparator.

2. 发明申请

US20220067250A1 VARIATION-AWARE DELAY FAULT TESTING 有权
公开(公告)号：US20220067250A1
公开(公告)日：2022-03-03
申请号：US17411346
申请日：2021-08-25
申请人： Duke University
发明人： Krishnendu Chakrabarty , Sanmitra Banerjee
IPC分类号： G06F30/31 , G06F30/3308
摘要： Variation-aware delay fault testing suitable for carbon nanotube field-effect transistor circuits can be accomplished using an electronic design automation tool that performs long path selection by generating random variation scenarios, wherein a random variation scenario (RVS) is an instance of an input netlist where values for a set of process parameters for each gate are chosen from a set of values for each process parameter of the set of process parameters for that gate, the set of values being sampled from a distribution of that particular process parameter for that gate and includes a nominal value for that particular process parameter; calculating a total delay through a path for each RVS; and selecting at least two paths having highest total delays for each fault site under random variations of the RVSs. Delay test patterns can then be generated for the selected paths.

3. 发明授权

US09720036B2 Signal tracing using on-chip memory for in-system post-fabrication debug 有权
公开(公告)号：US09720036B2
公开(公告)日：2017-08-01
申请号：US14461528
申请日：2014-08-18
申请人： DUKE UNIVERSITY
发明人： Sergej Deutsch , Krishnendu Chakrabarty
IPC分类号： G01R31/317 , G06F11/34 , G06F11/36
CPC分类号： G01R31/31703 , G01R31/31705 , G06F11/348 , G06F11/3636
摘要： A post-fabrication debug and on-line error checking framework for 2D- and 3D-ICs with integrated memories is described. A design-for-debug (DfD) architecture can include, for an IC with on-chip memory, a debug module connected to a functional bus of the IC. The debug module receives trace data for an interval, generates compact signatures based on the received data, and compares these signatures to expected signatures. Intervals containing erroneous trace data can be identified by the debug module and stored in on-chip memory. A single iteration of signal tracing for debug testing between automated test equipment and the IC is possible.

4. 发明授权

US08832608B1 Retiming-based design flow for delay recovery on inter-die paths in 3D ICs 有权
标题翻译：基于重定时的设计流程，用于3D IC中的管芯间路径上的延迟恢复
公开(公告)号：US08832608B1
公开(公告)日：2014-09-09
申请号：US13919022
申请日：2013-06-17
申请人： Duke University
发明人： Krishnendu Chakrabarty , Brandon Noia
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/14 , G06F2217/84
摘要： A three dimensional (3D) stacked integrated circuit (IC) design-for-Testing (DfT) die-level wrapper boundary register having a bypass mode and design-level DfT delay recovery techniques are provided. Die wrappers that contain boundary registers at the interface between dies can be inserted into 3D ICs where the boundary registers include a gated scan flop with a bypass line passing the functional input to a through-silicon-via (TSV) in a manner avoiding the clocked stages of the gated scan flop during functional operation. A retiming process can be applied during design layout using a simulation/routing tool or standalone program to recover the additional delay added to the TSV paths by the DfT insertion. Retiming can be performed at both die and stack level, and in further embodiments, logic redistribution across adjacent dies of the stack can be performed for further delay optimization.
摘要翻译：提供了具有旁路模式和设计级DfT延迟恢复技术的三维（3D）堆叠集成电路（IC）设计测试（DfT）晶粒级封装边界寄存器。在芯片之间的接口处包含边界寄存器的包装器可以插入到3D IC中，其中边界寄存器包括门控扫描触发器，旁路线将功能输入通过穿通硅通孔（TSV），以避免时钟功能运行期间门控扫描触发器的阶段。可以使用仿真/路由工具或独立程序在设计布局期间应用重新定时过程，以通过DfT插入恢复添加到TSV路径的附加延迟。可以在管芯和堆叠级别执行重新定时，并且在另外的实施例中，可以执行跨堆叠的相邻管芯的逻辑重新分配用于进一步的延迟优化。

5. 发明授权

US10444279B2 Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels 有权
公开(公告)号：US10444279B2
公开(公告)日：2019-10-15
申请号：US15266744
申请日：2016-09-15
申请人： DUKE UNIVERSITY
发明人： Krishnendu Chakrabarty , Sergej Deutsch
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/26
摘要： A design for test (DfT) architecture is provided that enables pre-bond parametric testing of through-silicon vias (TSVs). A grouping of N number of input/output (I/O) segments are configured to receive a test signal in a feedback loop, where each I/O segment includes one or more buffers (or inverters) and a TSV connected at one end to the one or more buffers. The TSV acts as a shunt-connected capacitor—when defect free—and includes a load resistance when the TSV contains a defect. Each I/O segment can also include one or two multiplexers to control whether the I/O segment receives a test or functional signal and, optionally, whether the I/O segment is bypassed or included in the ring oscillator. The varying loads caused by the defects cause variations in the delay across the buffers (or inverters) of an I/O segment that can be detected in the output signal.

6. 发明授权

US09864007B2 Software-based self-test and diagnosis using on-chip memory 有权
公开(公告)号：US09864007B2
公开(公告)日：2018-01-09
申请号：US14265501
申请日：2014-04-30
申请人： DUKE UNIVERSITY
发明人： Sergej Deutsch , Krishnendu Chakrabarty
IPC分类号： G01R27/28 , G01R31/00 , G01R31/14 , G01R31/3185 , G01R31/28 , G06F11/263 , G11C29/36 , G11C29/40 , G11C29/44 , G11C29/56 , G11C5/04
CPC分类号： G01R31/318547 , G01R31/2834 , G06F11/263 , G11C5/04 , G11C29/36 , G11C29/40 , G11C29/44 , G11C29/4401 , G11C29/56004
摘要： Embedded processor-based self-test and diagnosis using the compressed test data is described for ICs having on-chip memory. Techniques for compressing the test data before the compressed test data is transferred to a device under test (DUT) are also described. A modified LZ77 algorithm can be used to compress strings of test data in which don't care bits are handled by assigning a value to the don't care bits according to a longest match in the window as the data is being encoded. The compressed test data can be decompressed at the DUT using a software program transferred by the automated test equipment (ATE) to the DUT with the compressed test data. Decompression and diagnostics can be carried out at the DUT using an embedded processor and the on-chip memory. Results from the diagnostics can be read by the ATE.

7. 发明授权

US09482720B2 Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels 有权
标题翻译：使用环形振荡器和多个电压电平的非侵入性前置键合TSV测试
公开(公告)号：US09482720B2
公开(公告)日：2016-11-01
申请号：US13767089
申请日：2013-02-14
申请人： DUKE UNIVERSITY
发明人： Krishnendu Chakrabarty , Sergej Deutsch
IPC分类号： G01R31/26 , G01R31/3185
CPC分类号： G01R31/2853 , G01R31/2601 , G01R31/2894 , G01R31/318558
摘要： A design for test (DfT) architecture is provided that enables pre-bond parametric testing of through-silicon vias (TSVs). A grouping of N number of input/output (I/O) segments are configured to receive a test signal in a feedback loop, where each I/O segment includes one or more buffers (or inverters) and a TSV connected at one end to the one or more buffers. The TSV acts as a shunt-connected capacitor—when defect free—and includes a load resistance when the TSV contains a defect. Each I/O segment can also include one or two multiplexers to control whether the I/O segment receives a test or functional signal and, optionally, whether the I/O segment is bypassed or included in the ring oscillator. The varying loads caused by the defects cause variations in the delay across the buffers (or inverters) of an I/O segment that can be detected in the output signal.
摘要翻译：提供了一种用于测试（DfT）架构的设计，可以实现通硅通孔（TSV）的预键参数测试。 N个输入/输出（I / O）段的分组被配置为在反馈回路中接收测试信号，其中每个I / O段包括一个或多个缓冲器（或反相器）和一端连接到一个TSV 一个或多个缓冲区。当TSV包含缺陷时，TSV充当分流连接的电容器 - 当缺陷自由时包含负载电阻。每个I / O段还可以包括一个或两个多路复用器，以控制I / O段是否接收到测试或功能信号，以及可选地，该I / O段是否被绕过或包含在环形振荡器中。由缺陷引起的变化的负载导致可在输出信号中检测到的I / O段的缓冲器（或反相器）之间的延迟变化。

8. 发明授权

US10732221B2 Signal tracing using on-chip memory for in-system post-fabrication debug 有权
公开(公告)号：US10732221B2
公开(公告)日：2020-08-04
申请号：US15633486
申请日：2017-06-26
申请人： DUKE UNIVERSITY
发明人： Sergej Deutsch , Krishnendu Chakrabarty
IPC分类号： G01R31/317 , G06F11/34 , G06F11/36
摘要： A post-fabrication debug and on-line error checking framework for 2D- and 3D-ICs with integrated memories is described. A design-for-debug (DfD) architecture can include, for an IC with on-chip memory, a debug module connected to a functional bus of the IC. The debug module receives trace data for an interval, generates compact signatures based on the received data, and compares these signatures to expected signatures. Intervals containing erroneous trace data can be identified by the debug module and stored in on-chip memory. A single iteration of signal tracing for debug testing between automated test equipment and the IC is possible.

9. 发明申请

US20190302179A1 MULTI-LAYER INTEGRATED CIRCUITS HAVING ISOLATION CELLS FOR LAYER TESTING AND RELATED METHODS 审中-公开
公开(公告)号：US20190302179A1
公开(公告)日：2019-10-03
申请号：US16442920
申请日：2019-06-17
申请人： Duke University
发明人： Krishnendu Chakrabarty , Ran Wang
IPC分类号： G01R31/28 , H01L23/538 , H01L29/06
摘要： Multi-layer integrated circuits having isolation cells for layer testing and related methods are disclosed. According to an aspect, an integrated circuit includes multiple isolation cells. Example isolation cells include, but are not limited to, electronic fuses and tri-state flip-flops. The integrated circuit also includes a first layer having first and second sets of electronic components, the first set of electronic components being operatively connected to the second set of electronic components via the isolation cells. Further, the integrated circuit includes multiple transmission gates associated with the isolation cells. The integrated circuit also includes a second layer having electrical circuitry operatively connected to the electronic components of the first layer. The electrical circuitry is configured to apply test patterns to the electronic components of the first layer. Further, the electrical circuitry is configured to receive test responses from the electronic components of the first layer through the vias.

10. 发明授权

US10338133B2 Multi-layer integrated circuits having isolation cells for layer testing and related methods 有权
公开(公告)号：US10338133B2
公开(公告)日：2019-07-02
申请号：US15497389
申请日：2017-04-26
申请人： Duke University
发明人： Krishnendu Chakrabarty , Ran Wang
IPC分类号： G01R31/3187 , G01R31/26 , G01R31/28 , H01L23/525 , H01L25/065 , H01L29/06 , H01L21/66 , H01L23/538 , G01R31/44 , H01L23/00
摘要： Multi-layer integrated circuits having isolation cells for layer testing and related methods are disclosed. According to an aspect, an integrated circuit includes first and second layers that each have one or more electronic components. One or more electronic components of each layer can be electrically connected by a first via and a second via. The integrated circuit also includes an isolation cell operatively connected between the first via and the second via. The isolation cell is configured to controllably break electrical connection between the first via and the second via subsequent to testing of the at least one electronic component of the second layer. Example isolation cells include, but are not limited to, electronic fuses and tri-state flip-flops.

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