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1. 发明授权

US08332849B2 Paravirtualization acceleration through single root I/O virtualization 有权
标题翻译：通过单根I / O虚拟化实现半虚拟化加速
公开(公告)号：US08332849B2
公开(公告)日：2012-12-11
申请号：US12454626
申请日：2009-05-20
申请人： Richard L. Solomon , Timothy E. Hoglund
发明人： Richard L. Solomon , Timothy E. Hoglund
IPC分类号： G06F9/455 , G06F3/00
CPC分类号： G06F9/546 , G06F9/5061 , G06F2209/548
摘要： The present invention is directed to an information handling system device for operatively coupling with a device implementing Input/Output (I/O) virtualization for data transmission. The information handling system device may be configured for executing an operating system control program to manage one or more guest operating systems on the information handling system device. The operating system control program may include a paravirtualization driver for formulating a work queue entry according to the I/O virtualization of the device. Data may be transmitted between the one or more guest operating systems and the device via the paravirtualization driver.
摘要翻译：本发明涉及一种用于与实现用于数据传输的输入/输出（I / O）虚拟化的设备可操作地耦合的信息处理系统设备。信息处理系统设备可以被配置为执行操作系统控制程序来管理信息处理系统设备上的一个或多个客户操作系统。操作系统控制程序可以包括用于根据设备的I / O虚拟化来制定工作队列条目的半虚拟化驱动器。可以经由半虚拟化驱动器在一个或多个客户操作系统和设备之间传送数据。

2. 发明授权

US07007122B2 Method for pre-emptive arbitration 失效
标题翻译：先发制人的仲裁方法
公开(公告)号：US07007122B2
公开(公告)日：2006-02-28
申请号：US10306237
申请日：2002-11-27
申请人： Richard L. Solomon , Robert E. Ward
发明人： Richard L. Solomon , Robert E. Ward
IPC分类号： G06F12/00 , G06F13/14 , G06F13/38
CPC分类号： G06F13/4031
摘要： An interface system capable of providing pre-emptive arbitration among multiple agents comprises an interface including at least a first agent and a second agent which share the interface for transferring data, the second agent having priority over the first agent for access to the interface. A pre-emptive arbiter provides arbitration between the first agent and the second agent when at least one of a first transfer request signal is asserted by the first agent for requesting access to the interface by the first agent and a second transfer request signal is asserted by the second agent for requesting access to the interface by the second agent. The pre-emptive arbiter is capable of synthesizing a transfer completion signal on the interface for preempting access of the first agent to the interface so that access may be granted to the second agent.
摘要翻译：能够在多个代理之间提供优先仲裁的接口系统包括包括共享用于传送数据的接口的至少第一代理和第二代理的接口，所述第二代理优先于所述第一代理以访问所述接口。当第一代理确认第一传输请求信号的第一传送请求信号中的至少一个请求由第一代理接入该接口时，优先仲裁器提供第一代理和第二代理之间的仲裁，并且第二传输请求信号被第一代理断言用于请求由第二代理访问该接口的第二代理。优先仲裁器能够在接口上合成传送完成信号，以便抢占第一代理程序访问接口，以便可以向第二代理程序授予访问权限。

3. 发明授权

US06941427B2 Method and apparatus for improving queue traversal time 有权
标题翻译：提高队列遍历时间的方法和装置
公开(公告)号：US06941427B2
公开(公告)日：2005-09-06
申请号：US10324969
申请日：2002-12-20
申请人： Richard L. Solomon , Jill A. Thomas , Robert E. Ward
发明人： Richard L. Solomon , Jill A. Thomas , Robert E. Ward
IPC分类号： G06F12/00 , G06F13/10
CPC分类号： G06F13/102 , G06F2213/0024
摘要： A method and apparatus for traversing a queue of commands through part or all of the queue by selecting only the commands that need to be reissued. Commands to be reissued are labeled or designated as valid. The method may be practiced by setting a next valid address pointer in all queue entries. Queue traversal may be forward, backward, or bi-directional.
摘要翻译：通过仅选择需要重新发布的命令来遍历部分或全部队列的命令队列的方法和装置。要重新发行的命令被标记或指定为有效。该方法可以通过在所有队列条目中设置下一个有效的地址指针来实现。队列遍历可以是前向，后向或双向。

4. 发明申请

US20090257451A1 Method and apparatus to align and standardize packet based parallel interfaces 有权
标题翻译：调整和标准化基于数据包的并行接口的方法和装置
公开(公告)号：US20090257451A1
公开(公告)日：2009-10-15
申请号：US12082380
申请日：2008-04-10
申请人： Eugene Saghi , Richard L. Solomon , Robert E. Ward
发明人： Eugene Saghi , Richard L. Solomon , Robert E. Ward
IPC分类号： H04L29/02
CPC分类号： G06F13/385 , H04L1/0061
摘要： A packet alignment system for pre-processing/aligning incoming packets may comprise one or more registers for receiving control signals and data signals. An aligner may cyclically shift said data signals to form a plurality of shifted data words. A plurality of pipe registers may collect and generate an adjusted control signal for each one of the plurality of shifted data words. A filtering logic may identify one of the plurality of shifted data words as a desired aligned data word. The filter logic may also be configured for registering header data, payload data and ECRC data contained in the desired aligned data word in a header register, a payload register and an ECRC register, respectively. An output interface may generate an outgoing signal and provide data from at least one of the header register, the payload register and the ECRC register.
摘要翻译：用于预处理/对准输入分组的分组对准系统可以包括用于接收控制信号和数据信号的一个或多个寄存器。对准器可循环移位所述数据信号以形成多个移位数据字。多个管道寄存器可以针对多个移位数据字中的每一个收集并产生经调整的控制信号。滤波逻辑可以将多个移位的数据字中的一个识别为期望对准的数据字。滤波器逻辑还可以被配置用于分别在头部寄存器，有效载荷寄存器和ECRC寄存器中注册包含在期望对准的数据字中的头部数据，有效载荷数据和ECRC数据。输出接口可以产生输出信号并且从头部寄存器，有效载荷寄存器和ECRC寄存器中的至少一个提供数据。

5. 发明授权

US07216194B2 Methods and systems for improving delayed read handling 有权
标题翻译：改进延迟读取处理的方法和系统
公开(公告)号：US07216194B2
公开(公告)日：2007-05-08
申请号：US10409569
申请日：2003-04-08
申请人： Richard L. Solomon , Jill A. Thomas
发明人： Richard L. Solomon , Jill A. Thomas
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F2213/0024
摘要： Methods and systems for improving delayed read handling in a loop of delayed commands among a larger set of commands in a queue of commands are disclosed. In general, when commands in a delayed loop are completed out of order, “holes” are left in the command queue. Skipping over such “holes” consumes multiple clock cycles before another command can be issued, as each “hole” must be examined first in order to determine that it no longer contains a valid read command. A loop of delayed read commands can thus be created from among a larger set of commands in a queue of commands with each command entry having a pointer to the next valid command. Valid delayed read commands in the loop of commands can then be processed by automatically advancing between any two valid delayed read commands among the loop of commands. In this manner, the time to advance between any two commands in the delayed read loop is constant and PCI read performance thereof can be dramatically improved.
摘要翻译：公开了一种用于在命令队列中的较大命令集中的延迟命令循环中延迟读取处理的方法和系统。一般来说，当延迟循环中的命令按顺序完成时，命令队列中留下“孔”。跳过这样的“空穴”可以在发出另一个命令之前消耗多个时钟周期，因为必须首先检查每个“孔”，以确定它不再包含有效的读取命令。因此，可以从命令队列中的更大的一组命令中创建延迟读取命令的循环，其中每个命令条目具有指向下一个有效命令的指针。命令循环中有效的延迟读取命令可以通过在命令循环中的任意两个有效的延迟读取命令之间自动进行处理。以这种方式，在延迟读取循环中的任何两个命令之间进行的时间是恒定的，并且可以显着提高其PCI读取性能。

6. 发明授权

US06948139B2 Method for combining states 失效
标题翻译：组合状态的方法
公开(公告)号：US06948139B2
公开(公告)日：2005-09-20
申请号：US10326717
申请日：2002-12-19
申请人： Richard L. Solomon
发明人： Richard L. Solomon
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for combining states of a state machine employs manipulation of case statements in the RTL code implementing the state machine to allow selectable state combinations without duplication of code so that errors inherent in maintaining duplicate copies of the same RTL code may be eliminated.
摘要翻译：用于组合状态机的状态的方法采用对实现状态机的RTL代码中的情况语句的操作，以允许可选状态组合而不复制代码，从而可以消除维护相同RTL代码的重复副本所固有的错误。

7. 发明授权

US4043775A Air lock filter system 失效
标题翻译：气锁过滤系统
公开(公告)号：US4043775A
公开(公告)日：1977-08-23
申请号：US644656
申请日：1975-12-29
申请人： Richard L. Solomon
发明人： Richard L. Solomon
IPC分类号： B01D46/00 , B01D46/24 , B01D46/04
CPC分类号： B01D46/2411 , B01D46/0068 , B01D46/4272 , B01D2273/20
摘要： There is disclosed an air lock filter system for separating solids from gases at temperatures up to about 1200.degree. F. wherein the filter element is a rigid porous refractory tube in an air vent for a pressure vessel. The filter element is located so that gas under pressure introduced into the vessel backwashes the filter element.
摘要翻译：公开了一种用于在高达约1200°F的温度下从气体中分离固体的气密过滤系统。其中过滤元件是用于压力容器的通风口中的刚性多孔耐火管。过滤元件被定位成使得在压力下被引入容器的气体反冲洗过滤元件。

8. 发明授权

US07725640B2 Adapter card replay buffer for system fault analysis 有权
标题翻译：适配卡重放缓冲区用于系统故障分析
公开(公告)号：US07725640B2
公开(公告)日：2010-05-25
申请号：US12148308
申请日：2008-04-18
申请人： Richard L. Solomon
发明人： Richard L. Solomon
IPC分类号： G06F13/00
CPC分类号： G06F13/385 , G06F11/0745 , G06F11/0766
摘要： An adapter card for directing an information handling system (or another device) device to copy one or more data packets buffered in its memory may include an interface core. The interface core may comprise an electric circuit including electronic components and control logic for interfacing with the information handling system device. The adapter card may include a front end data channel coupled with the interface core for transmitting a data packet between the electronic components and the information handling system device. The adapter card may buffer a data packet according to a particular interface format and/or may include a buffer for storing the data packet. The adapter card may include control logic configured to direct the information handling system device to copy the data packets buffered in the memory of the adapter card.
摘要翻译：用于引导信息处理系统（或另一设备）设备来复制缓冲在其存储器中的一个或多个数据分组的适配器卡可以包括接口核心。接口芯可以包括电路，其包括用于与信息处理系统设备接口的电子部件和控制逻辑。适配器卡可以包括与接口核心耦合的前端数据信道，用于在电子部件和信息处理系统装置之间传送数据包。适配器卡可以根据特定接口格式缓冲数据分组和/或可以包括用于存储数据分组的缓冲器。适配器卡可以包括被配置为引导信息处理系统设备复制缓冲在适配器卡的存储器中的数据分组的控制逻辑。

9. 发明授权

US07701977B2 Method and apparatus to align and standardize packet based parallel interfaces 有权
标题翻译：调整和标准化基于数据包的并行接口的方法和装置
公开(公告)号：US07701977B2
公开(公告)日：2010-04-20
申请号：US12082380
申请日：2008-04-10
申请人： Eugene Saghi , Richard L. Solomon , Robert E. Ward
发明人： Eugene Saghi , Richard L. Solomon , Robert E. Ward
IPC分类号： H04J3/00
CPC分类号： G06F13/385 , H04L1/0061
摘要： A packet alignment system for pre-processing/aligning incoming packets may comprise one or more registers for receiving control signals and data signals. An aligner may cyclically shift said data signals to form a plurality of shifted data words. A plurality of pipe registers may collect and generate an adjusted control signal for each one of the plurality of shifted data words. A filtering logic may identify one of the plurality of shifted data words as a desired aligned data word. The filter logic may also be configured for registering header data, payload data and ECRC data contained in the desired aligned data word in a header register, a payload register and an ECRC register, respectively. An output interface may generate an outgoing signal and provide data from at least one of the header register, the payload register and the ECRC register.
摘要翻译：用于预处理/对准输入分组的分组对准系统可以包括用于接收控制信号和数据信号的一个或多个寄存器。对准器可循环移位所述数据信号以形成多个移位数据字。多个管道寄存器可以针对多个移位数据字中的每一个收集并产生经调整的控制信号。滤波逻辑可以将多个移位的数据字中的一个识别为期望对准的数据字。滤波器逻辑还可以被配置用于分别在头部寄存器，有效载荷寄存器和ECRC寄存器中注册包含在期望对准的数据字中的头部数据，有效载荷数据和ECRC数据。输出接口可以产生输出信号并且从头部寄存器，有效载荷寄存器和ECRC寄存器中的至少一个提供数据。

10. 发明授权

US06873948B1 Method and apparatus for emulating a device within a data processing system 失效
标题翻译：用于在数据处理系统内模拟设备的方法和装置
公开(公告)号：US06873948B1
公开(公告)日：2005-03-29
申请号：US09082663
申请日：1998-05-21
申请人： Richard L. Solomon
发明人： Richard L. Solomon
IPC分类号： G06F9/455 , G06F13/00 , G06F13/10
CPC分类号： G06F13/105
摘要： A method and apparatus in a data processing system for mimicking a device attached to a bus. Signaling is detected on the bus indicating a request to access the device. The bus is then monitored for a response by the device. If a selected period of time passes without a response being made by the device, a response suitable to indicate the presence of the device is sent onto the bus.
摘要翻译：用于模拟连接到总线上的装置的数据处理系统中的方法和装置。在总线上检测到信号，指示访问设备的请求。然后监控总线的设备响应。如果经过选择的时间段而没有由设备作出响应，则适合于指示设备的存在的响应被发送到总线上。

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