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1. 发明授权

US09876477B2 Operational amplifier circuit 有权
公开(公告)号：US09876477B2
公开(公告)日：2018-01-23
申请号：US15150542
申请日：2016-05-10
申请人： FUJI ELECTRIC CO., LTD.
发明人： Motomitsu Iwamoto
IPC分类号： H03F3/45 , H03F3/30
CPC分类号： H03F3/45192 , H03F3/3001 , H03F3/45 , H03F3/45071 , H03F3/45179 , H03F3/45183 , H03F2203/45248 , H03F2203/45264 , H03F2203/45342 , H03F2203/45692
摘要： In a folded cascode operational amplifier circuit, a source is connected to a back gate in each of third and fourth transistors that are cascode-connected to first and second transistors, which are an electric current source that returns an electric current signal output by a differential pair of an input stage. In the third and fourth transistors, an active parasitic element exists due to its device structure. When a falling edge signal of a rectangular wave is input, and electric current is supplied to the source of the third transistor to increase its electric potential, electric current flows into the drain from the back gate via the active parasitic element in an on state, in order to rapidly charge a capacitor. Thereby, a fifth transistor turns on within a shorter time, in order to improve an internal slew rate.

2. 发明授权

US08922276B2 Auto-zero amplifier and feedback amplifier circuit using the auto-zero amplifier 有权
标题翻译：自动归零放大器和反馈放大器电路采用自动调零放大器
公开(公告)号：US08922276B2
公开(公告)日：2014-12-30
申请号：US13675162
申请日：2012-11-13
申请人： Fuji Electric Co., Ltd.
发明人： Motomitsu Iwamoto
IPC分类号： H03F1/02 , H03F3/45 , H03F1/34
CPC分类号： H03F3/45179 , H03F1/342 , H03F3/45183 , H03F3/45475 , H03F3/45968 , H03F3/45986 , H03F2203/45536 , H03F2203/45544 , H03F2203/45562 , H03F2203/45588 , H03F2203/45614 , H03F2203/45616 , H03F2203/45618 , H03F2203/45644 , H03F2203/45674 , H03F2203/45681 , H03F2203/45684 , H03F2203/45724
摘要： In aspects of the invention, at normal operation, an operational amplifier circuit has feedback applied from the output thereof to the input thereof so that currents equal to each other flow in differential pair transistors, respectively. While, in order that currents equal to each other may flow in the differential pair transistors, respectively, for compensating the difference in threshold voltages in the differential pair transistors, a voltage lower by a certain voltage difference than the voltage applied to the gate terminal of the transistor must be applied to the gate terminal of the transistor. From this, the switching of switches, when a virtual short circuit occurs, can make the output voltage of the operational amplifier circuit become a signal in which positive and negative rectangular ripples, with the values thereof being proportional to the value of the certain voltage difference, are superimposed on a true value.
摘要翻译：在本发明的方面中，在正常操作中，运算放大器电路具有从其输出到其输入端的反馈，使得彼此相等的电流分别在差分对晶体管中流动。而为了分别在差分对晶体管中流过彼此相等的电流，用于补偿差分对晶体管中的阈值电压的差异，电压比施加到栅极端子的电压低一定的电压差晶体管必须施加到晶体管的栅极端子。由此，当虚拟短路发生时，开关的切换可以使运算放大器电路的输出电压成为正和负矩形波纹的信号，其值与特定电压差的值成正比，被叠加在真实值上。

3. 发明授权

US11196421B2 Logic circuit and circuit chip 有权
公开(公告)号：US11196421B2
公开(公告)日：2021-12-07
申请号：US17033907
申请日：2020-09-27
申请人： FUJI ELECTRIC CO., LTD.
发明人： Motomitsu Iwamoto
IPC分类号： H03K19/096 , H03K19/0944
摘要： Provided is a logic circuit comprising: a switch portion that includes one or more switching devices configured to be turned on and off in accordance with an input signal and is configured to generate an output signal with a logical value according to an operating state of the switching devices; and a clamp portion configured to clamp a voltage of the output signal, of a case where the logical value of the output signal is logic H. The switch portion may be arranged between an output line and a reference potential line, and the clamp portion may be arranged in parallel with the switch portion, between the output line and the reference potential line. The logic circuit may include a current suppression portion configured to suppress a current flowing through the clamp portion, when the logical value of the output signal is logic H.

4. 发明授权

US10396729B2 Differential circuit and operational amplifier 有权
公开(公告)号：US10396729B2
公开(公告)日：2019-08-27
申请号：US16021042
申请日：2018-06-28
申请人： FUJI ELECTRIC CO., LTD.
发明人： Motomitsu Iwamoto
IPC分类号： H03F3/45 , G11C5/14 , G05F1/56 , G11C7/06 , G11C29/02
摘要： A differential circuit including: a first MOS transistor and a second MOS transistor that constitute a differential pair; a determination unit to determine a level of a determination target signal that is based on at least one of differential inputs being input to gate of the first MOS transistor and a gate of the second MOS transistor; and a voltage changing unit to change a back gate voltage that is supplied to both back gates of the first MOS transistor and the second MOS transistor according to a determination result of the determination unit, and an OP-amp will be provided.

5. 发明授权

US10304645B2 Trimming apparatus 有权
公开(公告)号：US10304645B2
公开(公告)日：2019-05-28
申请号：US15373039
申请日：2016-12-08
申请人： FUJI ELECTRIC CO., LTD.
发明人： Motomitsu Iwamoto
IPC分类号： H01H37/76 , H03K19/21 , G11C19/28
摘要： A trimming apparatus for adjusting an electric property of a trimming object circuit. The trimming apparatus includes a data input pad that receives an input of serial data, a shift register that outputs parallel setting data by shifting the received serial data, a trimming data generating circuit, and a cutting control circuit that controls application of an electric signal to the trimming data generating circuit. The trimming data generating circuit includes a plurality of trimming elements, each having a conductive part cuttable by a flow of the electric signal, a plurality of pull-up resistors respectively connected to high potential sides of the trimming elements, and a plurality of switches respectively connected to low potential sides of the trimming elements. The trimming data generating circuit is configured to generate trimming data for the trimming object circuit by switching the plurality of switches in accordance with a level of the setting data.

6. 发明授权

US09667209B2 Amplifying device and offset voltage correction method 有权
公开(公告)号：US09667209B2
公开(公告)日：2017-05-30
申请号：US14884209
申请日：2015-10-15
申请人： FUJI ELECTRIC CO., LTD.
发明人： Motomitsu Iwamoto
IPC分类号： H03F3/45 , H03F3/217
CPC分类号： H03F3/2173 , H03F3/45183 , H03F3/45771 , H03F2200/375 , H03F2203/45044 , H03F2203/45674
摘要： An output voltage delay time caused by the relationship between offset voltage and input voltage is shortened. A single power supply amplifying device includes first and second amplifying units, a state detecting unit, and an offset voltage correcting unit. The first amplifying unit has differential pair transistors and amplifies the difference between input voltages. The second amplifying unit amplifies a first output voltage of the first amplifying unit. The state detecting unit detects a state where a negative offset voltage that causes a second output voltage of the second amplifying unit to be lower than the input voltage occurs, and a potential of the input voltage is lower than the absolute value of the negative offset voltage. The offset voltage correcting unit then corrects the negative offset voltage to a positive offset voltage that causes the second output voltage to be higher than the input voltage.

7. 发明授权

US09344047B2 Operational amplifier circuit 有权
标题翻译：运算放大器电路
公开(公告)号：US09344047B2
公开(公告)日：2016-05-17
申请号：US14231810
申请日：2014-04-01
申请人： FUJI ELECTRIC CO., LTD.
发明人： Motomitsu Iwamoto
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , H03F3/45219 , H03F2203/45352
摘要： In aspects of the invention, an operational amplifier circuit includes: an N-MOS auxiliary current source connected in parallel to the N-MOS differential pair, the N-MOS auxiliary current source turning ON when the N-MOS differential pair turns OFF caused by a decreased common mode input voltage given to the pair of voltage input terminals, drawing a current from the active load for the P-MOS differential pair. Aspects of the invention also include a P-MOS auxiliary current source connected in parallel to the P-MOS differential pair, the P-MOS auxiliary current source turning ON when the P-MOS differential pair turns OFF caused by an increased common mode input voltage given to the pair of voltage input terminals, delivering a current to the active load for the-N-MOS differential pair.
摘要翻译：在本发明的方面，运算放大器电路包括：与N-MOS差分对并联连接的N-MOS辅助电流源，N-MOS辅助电流源在N-MOS差动对断开时导通，降低的共模输入电压给一对电压输入端，从P-MOS差分对的有功负载中抽出电流。本发明的方面还包括与P-MOS差分对并联连接的P-MOS辅助电流源，当P-MOS差动对由于增加的共模输入电压而导致OFF时，P-MOS辅助电流源导通给予一对电压输入端子，为N-MOS差分对提供电流到有源负载。

8. 发明授权

US09130521B2 Operational amplifier circuit 有权
标题翻译：运算放大器电路
公开(公告)号：US09130521B2
公开(公告)日：2015-09-08
申请号：US14243084
申请日：2014-04-02
申请人： FUJI ELECTRIC CO., LTD.
发明人： Motomitsu Iwamoto
IPC分类号： H03F3/45
CPC分类号： H03F3/45219 , H03F2203/45244
摘要： Aspects of the invention include an operational amplifier circuit having a construction of a rail-to rail input folded circuit and includes an N-MOS differential pair composed of a pair of N-channel type MOS-FETs connected to a pair of voltage input terminals, and a P-MOS differential pair composed of a pair of P-channel type MOS-FETs connected to the pair of voltage input terminals. In some aspects, a comparator determines whether an common mode input voltage to the N-MOS differential pair and the P-MOS differential pair is higher than a half of a power supply voltage or not, and either one of the N-MOS differential pair and the P-MOS differential pair is selectively operated according to the comparison result. Active loads are provided separately for the N-MOS differential pair and for the P-MOS differential pair.
摘要翻译：本发明的方面包括具有轨到轨输入折叠电路的结构的运算放大器电路，并且包括由连接到一对电压输入端子的一对N沟道型MOS-FET组成的N-MOS差分对，以及由连接到所述一对电压输入端子的一对P沟道型MOS-FET构成的P-MOS差分对。在一些方面，比较器确定对N-MOS差分对和P-MOS差分对的共模输入电压是否高于电源电压的一半，并且N-MOS差分对中的任一个并且根据比较结果选择性地操作P-MOS差分对。为N-MOS差分对和P-MOS差分对分别提供有源负载。

9. 发明授权

US10771027B2 Operational amplifier circuit and current detection device using the same 有权
公开(公告)号：US10771027B2
公开(公告)日：2020-09-08
申请号：US16253479
申请日：2019-01-22
申请人： FUJI ELECTRIC CO., LTD.
发明人： Motomitsu Iwamoto
IPC分类号： H03F3/04 , H03F3/45 , G01R31/26 , H03K17/082 , G05F1/56 , G05F3/26 , G01R19/00
摘要： An operational amplifier circuit includes a potential control circuit connected between a current sense semiconductor element connected in parallel with a main semiconductor element and a current detection resistor. The potential control circuit controls an output potential of the current sense semiconductor element to be equal to that of the main semiconductor element. The potential control circuit includes a current control element controlling an output current of the current sense semiconductor element and an operational amplifier outputting a signal corresponding to an output potential difference between the current sense semiconductor element and the main semiconductor element to the current control element. An input offset voltage polarity determination unit determines a polarity of an input offset voltage of the operational amplifier according to the output potential difference. The polarity of the input offset voltage is controlled to be constant based on polarity determination of the input offset voltage.

10. 发明授权

US10756728B2 Insulated gate device drive apparatus 有权
公开(公告)号：US10756728B2
公开(公告)日：2020-08-25
申请号：US16699401
申请日：2019-11-29
申请人： FUJI ELECTRIC CO., LTD.
发明人： Takahiro Mori , Motomitsu Iwamoto
IPC分类号： H03K17/14 , H03K17/687 , H03K17/60
摘要： An insulated gate device drive apparatus for driving an insulated gate device by using a charging current outputted from a totem-pole output circuit constituted by a high-side output transistor and a low-side output transistor. The insulated gate device drive apparatus includes a charging current correction circuit configured to perform correction to increase the charging current that is decreased by an increased voltage drop of high-side wiring resistance between a power supply and the high-side output transistor.

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