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1. 发明申请

US20180183395A1 ACTIVE INDUCTOR AND AMPLIFIER CIRCUIT 审中-公开
公开(公告)号：US20180183395A1
公开(公告)日：2018-06-28
申请号：US15699147
申请日：2017-09-08
申请人： Toshiba Memory Corporation
发明人： Yuta Tsubouchi , Junji Wadatsumi
IPC分类号： H03F3/45 , H03H11/48 , H03F1/02
CPC分类号： H03F3/45273 , H03F1/0205 , H03F3/45183 , H03F3/45219 , H03F2203/45021 , H03F2203/45034 , H03H11/48
摘要： According to an embodiment, an active inductor has a first conductivity type MOS transistor with a source that is connected to an electrical power source supply line and a drain that is connected to an output terminal. It has a capacitance between a gate of the first conductivity type MOS transistor and the electrical power source supply line. It has a diode element that is connected between a drain and a gate of the first conductivity type transistor. It has an electric current source that supplies a bias electric current in a forward direction to the diode element.

2. 发明授权

US09979363B2 Source driver including output buffer, display driving circuit, and operating method of source driver 有权
公开(公告)号：US09979363B2
公开(公告)日：2018-05-22
申请号：US15171080
申请日：2016-06-02
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Ju-Hyun Ko , Yong-joo Song , Jun-ho Song , Jin-chul Choi , Beop-hee Kim
IPC分类号： H03F3/45 , G09G3/20 , H03F3/30
CPC分类号： H03F3/45273 , G09G3/2092 , G09G2310/0248 , G09G2310/0254 , G09G2310/0291 , G09G2310/08 , G09G2330/021 , H03F3/3022 , H03F3/45219 , H03F3/45475 , H03F2203/45112 , H03F2203/45726
摘要： A source driver includes a buffer device including a plurality of buffers corresponding to a plurality of data lines, each of the plurality of buffers respectively including an amplifier configured to amplify an input signal and an output driver configured to output a driving signal to a corresponding data line among the plurality of data lines; and a switch device including a charge sharing switch configured to electrically connect the plurality of data lines to one another during a charge sharing operation, each of the amplifiers including a first current mirror having a reference current path including a first node and an output current path including a second node, and the first node of the reference current path and the second node of the output current path are electrically connected to each other during the charge sharing operation.

3. 发明授权

US09923522B2 Operational amplifier circuit and bias current supply method 有权
公开(公告)号：US09923522B2
公开(公告)日：2018-03-20
申请号：US15305462
申请日：2014-07-08
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： Takayuki Nakai
IPC分类号： H03F3/45 , H03F1/02
CPC分类号： H03F1/0233 , H03F1/0277 , H03F3/3028 , H03F3/45219 , H03F3/45475 , H03F3/45748 , H03F2200/261
摘要： Bias current is supplied to a first differential pair and a second differential pair from a first transistor being a single current source. Bias current is supplied to a third differential pair and a fourth differential pair from a second transistor being a single current source. An input voltage is at a power supply potential, and an input voltage is at a ground potential. When the second differential pair and the third differential pair are turned OFF, the bias current supplied from the first transistor flows to an output stage via the first differential pair, and the bias current supplied from the second transistor flows to the output stage via the fourth differential pair. Therefore, when the second differential pair and the third differential pair are turned OFF, a circuit current is kept constant, and a fluctuation in a frequency characteristic can be restrained.

4. 发明申请

US20170040959A1 APPARATUS AND METHOD FOR PRECHARGING A LOAD 有权
标题翻译：装载和预付货物的方法
公开(公告)号：US20170040959A1
公开(公告)日：2017-02-09
申请号：US14818126
申请日：2015-08-04
申请人： Analog Devices Global
发明人： Gerard Mora-Puchalt
IPC分类号： H03F3/217 , H03F1/02 , H03M1/12
CPC分类号： H03F3/2175 , H03F1/0205 , H03F1/303 , H03F3/2171 , H03F3/303 , H03F3/45179 , H03F3/45219 , H03F3/45748 , H03F3/45775 , H03F2200/231 , H03F2200/297 , H03F2203/45112 , H03F2203/45116 , H03F2203/45292 , H03F2203/45454 , H03M1/12
摘要： An output stage of a buffer or an amplifier connected to a switched capacitive load can operate in two phases to perform precharging and fine settling. The precharging and fine settling phases can be synchronized to the switching phases of the switched capacitive load connected to the amplifier. During the precharging phase, the output stage can be disconnected from the prior stages of the amplifier, and the output node of the amplifier can be connected to the switched capacitive load to precharge the capacitive load with the voltage already stored in the output stage. During the fine settling phase, the output stage can be reconnected to the prior stages of the amplifier, and the amplifier nodes can settle and get ready for sampling, which can occur at the end of the fine settling phase.
摘要翻译：连接到开关电容性负载的缓冲器或放大器的输出级可以分两个阶段进行，以执行预充电和精细的稳定。预充电和精细建立阶段可以与连接到放大器的开关电容负载的开关相位同步。在预充电阶段，输出级可以与放大器的前级断开，并且放大器的输出节点可以连接到开关容性负载，以便已经存储在输出级中的电压对电容性负载进行预充电。在精细建立阶段期间，输出级可以重新连接到放大器的前级，并且放大器节点可以稳定并准备好进行采样，这可以在微调阶段结束时发生。

5. 发明申请

US20170032760A1 OPERATIONAL AMPLIFYING CIRCUIT AND LIQUID CRYSTAL PANEL DRIVE DEVICE USING THE SAME 有权
标题翻译：操作放大电路和液晶板驱动装置
公开(公告)号：US20170032760A1
公开(公告)日：2017-02-02
申请号：US15291554
申请日：2016-10-12
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Kenji SHIMOMAKI
IPC分类号： G09G3/36 , G09G3/20 , H03F3/45
CPC分类号： G09G3/3696 , G09G3/2007 , G09G3/3688 , G09G2310/0291 , G09G2310/08 , H03F3/45219 , H03F2203/45124 , H03F2203/45248 , H03F2203/45461
摘要： An operational amplifier circuit includes: a first differential amplifier section containing a P-type differential pair of P-type transistors; a second differential amplifier section containing an N-type differential pair of N-type transistors; an intermediate stage connected with outputs of the first and second differential amplifier sections and containing a first current mirror circuit of P-type transistors, and a second current mirror circuit of N-type transistors; and an output stage configured to amplify an output of the intermediate stage in power. The first differential amplifier section includes a first current source and a first capacitance between sources of the P-type transistors of the P-type differential pair and a positive side power supply voltage. The second differential amplifier section includes a second current source and a second capacitance between sources of the N-type transistors of the N-type differential pair and a negative side power supply voltage.
摘要翻译：运算放大器电路包括：包含P型差分对的P型晶体管的第一差分放大器部分; 第二差分放大器部分，包含N型晶体管的N型差分对; 中间级与第一和第二差分放大器部分的输出相连并且包含P型晶体管的第一电流镜电路和N型晶体管的第二电流镜电路; 以及输出级，被配置为在功率中放大中间级的输出。第一差分放大器部分包括第一电流源和P型差分对的P型晶体管的源极与正侧电源电压之间的第一电容。第二差分放大器部分包括第二电流源和N型差分对的N型晶体管的源极和负侧电源电压之间的第二电容。

6. 发明申请

US20170032740A1 SOURCE DRIVER INCLUDING OUTPUT BUFFER, DISPLAY DRIVING CIRCUIT, AND OPERATING METHOD OF SOURCE DRIVER 有权
标题翻译：源驱动器，包括输出缓冲器，显示驱动电路和源驱动器的操作方法
公开(公告)号：US20170032740A1
公开(公告)日：2017-02-02
申请号：US15171080
申请日：2016-06-02
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Ju-Hyun KO , Yong-joo SONG , Jun-ho SONG , Jin-chul CHOI , Beop-hee KIM
IPC分类号： G09G3/3258 , G09G3/36 , H03F3/45
CPC分类号： H03F3/45273 , G09G3/2092 , G09G2310/0248 , G09G2310/0254 , G09G2310/0291 , G09G2310/08 , G09G2330/021 , H03F3/3022 , H03F3/45219 , H03F3/45475 , H03F2203/45112 , H03F2203/45726
摘要： A source driver includes a buffer device including a plurality of buffers corresponding to a plurality of data lines, each of the plurality of buffers respectively including an amplifier configured to amplify an input signal and an output driver configured to output a driving signal to a corresponding data line among the plurality of data lines; and a switch device including a charge sharing switch configured to electrically connect the plurality of data lines to one another during a charge sharing operation, each of the amplifiers including a first current mirror having a reference current path including a first node and an output current path including a second node, and the first node of the reference current path and the second node of the output current path are electrically connected to each other during the charge sharing operation.
摘要翻译：源驱动器包括缓冲器装置，其包括对应于多个数据线的多个缓冲器，所述多个缓冲器中的每一个缓冲器分别包括被配置为放大输入信号的放大器和被配置为将驱动信号输出到相应数据的输出驱动器在多条数据线之间; 以及开关装置，其包括电荷共享开关，其被配置为在电荷共享操作期间将所述多个数据线彼此电连接，所述放大器包括具有参考电流路径的第一电流镜，所述参考电流路径包括第一节点和输出电流路径包括第二节点，并且在电荷共享操作期间，参考电流路径的第一节点和输出电流路径的第二节点彼此电连接。

7. 发明申请

US20160173065A1 HALF-POWER BUFFER AND/OR AMPLIFIER 有权
标题翻译：高功率缓冲器和/或放大器
公开(公告)号：US20160173065A1
公开(公告)日：2016-06-16
申请号：US14820182
申请日：2015-08-06
申请人： Dongbu HiTek Co., Ltd.
发明人： Mun Gyu KIM , Sun Young LEE , Jeong Tae PARK , Seung Jin YEO
IPC分类号： H03K3/012 , H03F3/21
CPC分类号： H03K3/012 , H03F3/211 , H03F3/45219 , H03F3/72 , H03F2200/555 , H03K19/0013 , H03K19/018528
摘要： Disclosed is a half-power buffer/amplifier. The half-power buffer/amplifier includes first and second amplifying blocks respectively corresponding to first and second channels, a first output buffer unit controlled by an output from the first amplifying block, and a second output buffer unit controlled by an output from the second amplifying block. Each of the first and second amplifying blocks includes an input unit configured to amplify a first input signal, thereby outputting first and second currents, and an amplifying unit including a first current mirror, a second current mirror, and a bias unit connected between the first current mirror and the second mirror. Nodes in the first and second amplifying blocks are selectively connected to source/drain terminals of transistors in the first and second amplifying blocks in response to a control signal.
摘要翻译：公开了一种半功率缓冲器/放大器。半功率缓冲器/放大器包括分别对应于第一和第二通道的第一和第二放大块，由第一放大块的输出控制的第一输出缓冲器单元和由第二放大器的输出控制的第二输出缓冲器单元块。第一和第二放大块中的每一个包括被配置为放大第一输入信号，从而输出第一和第二电流的输入单元，以及包括第一电流镜，第二电流镜和偏置单元的放大单元，电流镜和第二镜。响应于控制信号，第一和第二放大块中的节点选择性地连接到第一和第二放大块中的晶体管的源极/漏极端子。

8. 发明授权

US09225304B1 Single-stage folded cascode buffer amplifiers with analog comparators 有权
标题翻译：具有模拟比较器的单级折叠共源共栅放大器
公开(公告)号：US09225304B1
公开(公告)日：2015-12-29
申请号：US14522678
申请日：2014-10-24
申请人： SanDisk 3D LLC
发明人： Vincent Lai
IPC分类号： H03F3/45 , H03F1/30
CPC分类号： H03F1/308 , G11C11/5642 , G11C27/005 , H03F3/3022 , H03F3/45183 , H03F3/45219 , H03F2200/45 , H03F2200/78 , H03F2203/30096 , H03F2203/30129 , H03F2203/45116
摘要： A single-stage folded cascode buffer including an amplifier, a first analog comparator, a second analog comparator, a first transistor, and a second transistor, The amplifier includes a first input terminal, a second input terminal, and an output terminal coupled to the second input terminal of the amplifier. The first analog comparator includes a first input terminal, a second input terminal, and an output terminal. The second analog comparator includes a first input terminal, a second input terminal, and an output terminal. The first transistor includes a first terminal, a second terminal coupled to the output terminal of the first analog comparator, and a third terminal coupled to the output terminal of the amplifier. The second transistor includes a first terminal coupled to the output terminal of the amplifier, a second terminal coupled to the output terminal of the second analog comparator, and a third terminal.
摘要翻译：包括放大器，第一模拟比较器，第二模拟比较器，第一晶体管和第二晶体管的单级折叠共源共栅缓冲器。放大器包括第一输入端子，第二输入端子和耦合到第二晶体管的输出端子放大器的第二输入端。第一模拟比较器包括第一输入端，第二输入端和输出端。第二模拟比较器包括第一输入端，第二输入端和输出端。第一晶体管包括第一端子，耦合到第一模拟比较器的输出端子的第二端子和耦合到放大器的输出端子的第三端子。第二晶体管包括耦合到放大器的输出端的第一端子，耦合到第二模拟比较器的输出端的第二端子和第三端子。

9. 发明授权

US08810288B2 Output buffer 有权
标题翻译：输出缓冲区
公开(公告)号：US08810288B2
公开(公告)日：2014-08-19
申请号：US13786481
申请日：2013-03-06
申请人： Novatek Microelectronics Corp.
发明人： Chun-Hung Chen
IPC分类号： H03B1/00
CPC分类号： H03K3/012 , H03F3/3023 , H03F3/45183 , H03F3/45219 , H03F2203/45634 , H03F2203/45674 , H03K19/00
摘要： An output buffer is disclosed. The output buffer includes an input-stage circuit, an output-stage circuit and a compensation circuit. The compensation circuit includes a capacitor, a first switch, a second switch, a third switch, and a fourth switch. The input-stage circuit receives a differential input signal and outputting a response signal. The output-stage circuit receives the response signal and outputting an output signal. The first switch controls a connection between the input-stage circuit and a first terminal of the capacitor. The second switch controls the connection between an output terminal of the compensation circuit and a second terminal of the capacitor. The third switch controls the connection between the input-stage circuit and the second-terminal of the capacitor. The forth switch controls the connection between the output terminal of the compensation circuit and the first terminal of the capacitor.
摘要翻译：公开了输出缓冲器。输出缓冲器包括输入级电路，输出级电路和补偿电路。补偿电路包括电容器，第一开关，第二开关，第三开关和第四开关。输入级电路接收差分输入信号并输出响应信号。输出级电路接收响应信号并输出输出信号。第一开关控制输入级电路和电容器的第一端之间的连接。第二开关控制补偿电路的输出端子和电容器的第二端子之间的连接。第三开关控制输入级电路和电容器的第二端之间的连接。第四开关控制补偿电路的输出端子与电容器的第一端子之间的连接。

10. 发明申请

US20140159814A1 DIFFERENTIAL RECEIVER 有权
标题翻译：差异接收器
公开(公告)号：US20140159814A1
公开(公告)日：2014-06-12
申请号：US14048750
申请日：2013-10-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Weicheng Zhang , Huanzhang Huang , Yanli Fan , Mark W. Morgan
IPC分类号： H03F3/45
CPC分类号： H03F3/45219 , H03F3/45632 , H03F2203/45466 , H03F2203/45646 , H03F2203/45648
摘要： A differential receiver with reduced common mode induced propagation delay variance. One implementation of a differential receiver includes a first differential amplifier, a second differential amplifier, and a first current source. The first differential amplifier includes a first transistor pair. The second differential amplifier includes a second transistor pair. The first current source is coupled to a drain node of a first transistor of the first transistor pair. The first current source is configured to generate a variable first current at the drain node as of function of a sum of a variable tail current of the first differential amplifier and a variable tail current of the second differential amplifier.
摘要翻译：具有降低的共模感应传播延迟方差的差分接收机。差分接收机的一个实施方式包括第一差分放大器，第二差分放大器和第一电流源。第一差分放大器包括第一晶体管对。第二差分放大器包括第二晶体管对。第一电流源耦合到第一晶体管对的第一晶体管的漏极节点。第一电流源被配置为根据第一差分放大器的可变尾电流和第二差分放大器的可变尾电流的和的函数，在漏极节点处产生可变的第一电流。

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