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    • 4. 发明授权
    • Analyzing EM performance during IC manufacturing
    • 分析IC制造过程中的EM性能
    • US08917104B2
    • 2014-12-23
    • US13222306
    • 2011-08-31
    • Fen ChenRoger A. DufresneKai D. FengRichard J. St-Pierre
    • Fen ChenRoger A. DufresneKai D. FengRichard J. St-Pierre
    • G01R31/3187G01R31/28
    • G01R31/2858
    • A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure.
    • 用于监测电迁移(EM)性能的测试结构,系统和方法。 描述了包括测试结构阵列的系统,其中每个测试结构包括:具有四点电阻测量的EM电阻器,其中第一和第二端子提供电流输入,第三和第四端子提供电压测量; 耦合到所述EM电阻器的第一端子以提供测试电流的第一晶体管; 由一对开关晶体管获得的电压测量,其栅极由选择开关控制,并且其漏极用于在第三和第四端子处提供电压测量。 还包括用于选择性地激活测试结构阵列之一的选择开关的解码器; 以及用于输出所选择的测试结构的电压测量的一对输出。
    • 8. 发明授权
    • Thermo-mechanical cleavable structure
    • 热机械可切割结构
    • US08018017B2
    • 2011-09-13
    • US10905905
    • 2005-01-26
    • Fen ChenCathryn J. ChristiansenRichard S. KontraTom C. LeeAlvin W. StrongTimothy D. SullivanJoseph E. Therrien
    • Fen ChenCathryn J. ChristiansenRichard S. KontraTom C. LeeAlvin W. StrongTimothy D. SullivanJoseph E. Therrien
    • H01L31/058
    • H01L23/5256H01L2924/0002H01L2924/00
    • A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.
    • 提供了一种热机械可切割结构,可用作集成电路的可编程保险丝。 如应用于可编程保险丝,热机械可切割结构包括与热机械应力源相邻的导电可切割层。 当电通过可切割层时,可切割层和热机械应力器被加热并且气体从热机械应力源逸出。 气体将热机械应力局部绝缘,导致邻近热机械应力的气泡局部熔化,形成裂开位置的可切割结构。 熔化还中断当前通过可切割结构的流动,因此可切割结构冷却和收缩。 热机械应力还由于由其产生的气体引起的相变而收缩。 当热机械可裂解结构冷却时,裂解位置膨胀,导致间隙永久形成。
    • 9. 发明授权
    • Method of forming metal ion transistor
    • 形成金属离子晶体管的方法
    • US07998828B2
    • 2011-08-16
    • US12725817
    • 2010-03-17
    • Fen ChenArmin Fischer
    • Fen ChenArmin Fischer
    • H01L21/34H01L29/12H01L27/148H01L51/40H01L21/335H01L21/8232H01L21/339H01L21/00H01L21/84H01L21/76H01L21/20H01L21/36
    • H01L45/00
    • A method of forming a metal ion transistor comprises forming a first electrode in a first isolation layer; forming a second isolation layer over the first isolation layer; forming a first cell region of a low dielectric constant (low-k) dielectric over the first electrode in the second isolation layer, the first cell region isolated from the second isolation layer; forming a cap layer over the second isolation layer and the first cell region, at least thinning the cap layer over the first cell region; depositing a layer of the low-k dielectric over the second isolation layer and the first cell region; forming metal ions in the low-k dielectric layer; patterning the low-k dielectric layer to form a second cell region; sealing the second cell region using a liner; and forming a second electrode contacting the second cell region and a third electrode contacting the second cell region.
    • 一种形成金属离子晶体管的方法包括在第一隔离层中形成第一电极; 在所述第一隔离层上形成第二隔离层; 在所述第二隔离层中的所述第一电极上形成低介电常数(低k)电介质的第一电池区,所述第一电池区与所述第二隔离层隔离; 在所述第二隔离层和所述第一单元区域上形成盖层,至少使所述盖层在所述第一单元区域上变薄; 在所述第二隔离层和所述第一单元区域上沉积所述低k电介质层; 在低k电介质层中形成金属离子; 图案化低k电介质层以形成第二电池区; 使用衬垫密封第二电池区域; 以及形成与第二单元区域接触的第二电极和与第二单元区域接触的第三电极。
    • 10. 发明授权
    • Device structures with a self-aligned damage layer and methods for forming such device structures
    • 具有自对准损伤层的装置结构和用于形成这种装置结构的方法
    • US07795679B2
    • 2010-09-14
    • US12178766
    • 2008-07-24
    • Ethan H. CannonFen Chen
    • Ethan H. CannonFen Chen
    • H01L31/0392H01L21/8238H01L21/336
    • H01L29/0653H01L21/26506H01L29/6659H01L29/66659H01L29/7842H01L29/7848
    • Device structures with a self-aligned damage layer and methods of forming such device structures. The device structure first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate. A third doped region of opposite conductivity type laterally separates the first doped region from the second doped region. A gate structure is disposed on a top surface of the substrate and has a vertically stacked relationship with the third doped region. A first crystalline damage layer is defined within the semiconductor material of the substrate. The first crystalline damage layer has a first plurality of voids surrounded by the semiconductor material of the substrate. The first doped region is disposed vertically between the first crystalline damage layer and the top surface of the substrate. The first crystalline damage layer does not extend laterally into the third doped region.
    • 具有自对准损伤层的装置结构和形成这种装置结构的方法。 该器件结构是限定在衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。 相反导电类型的第三掺杂区域将第一掺杂区域与第二掺杂区域横向分离。 栅极结构设置在衬底的顶表面上,并且与第三掺杂区域具有垂直堆叠的关系。 第一晶体损伤层被限定在衬底的半导体材料内。 第一晶体损伤层具有由衬底的半导体材料包围的第一多个空隙。 第一掺杂区域垂直地设置在第一晶体损伤层和衬底的顶表面之间。 第一晶体损伤层不横向延伸到第三掺杂区域。