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1. 发明授权

US07809961B2 Standby mode for power management 有权
标题翻译：待机模式进行电源管理
公开(公告)号：US07809961B2
公开(公告)日：2010-10-05
申请号：US11559388
申请日：2006-11-13
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost
IPC分类号： G06F1/00 , G06F3/038 , H04B7/185 , H04B1/04 , H04B1/16 , H04B7/00 , H04B1/38 , G09G3/18 , G11C5/14
CPC分类号： G06F1/3237 , G06F1/3228 , Y02D10/128 , Y02D50/20
摘要： An apparatus and method for controlling standby mode in an electronic device. In standby mode, power and clock signals are reduced or stopped to conserve power. The apparatus includes an initiator module coupled to a power and clock control module (PCCM). When the initiator module meets conditions for standby mode, the initiator module sends a standby signal to the PCCM and does not interact with other initiator, target, or interconnect modules. When the PCCM communicates a wait signal, the initiator module enters standby mode. When the initiator module detects a wakeup event, the standby signal is deactivated. In this state, the initiator module may process information but may not interact with other modules. When the PCCM deactivates the wait signal and returns power and clock signal to steady state levels, initiator module may resume normal operation.
摘要翻译：一种用于控制电子设备中的待机模式的装置和方法。在待机模式下，电源和时钟信号被减少或停止以节省电力。该装置包括耦合到电源和时钟控制模块（PCCM）的启动器模块。当启动器模块满足待机模式条件时，启动器模块向PCCM发送备用信号，不与其他启动器，目标或互连模块进行交互。当PCCM通信等待信号时，启动器模块进入待机模式。当启动器模块检测到唤醒事件时，待机信号被禁用。在这种状态下，启动器模块可以处理信息，但是可能不与其他模块进行交互。当PCCM关闭等待信号并将电源和时钟信号恢复到稳定状态时，启动器模块可以恢复正常工作。

2. 发明申请

US20070130482A1 Idle Mode for Power Management 审中-公开
标题翻译：电源管理空闲模式
公开(公告)号：US20070130482A1
公开(公告)日：2007-06-07
申请号：US11559387
申请日：2006-11-13
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： An apparatus and method for controlling idle mode in an electronic device. In idle mode, power and clock signals are reduced or stopped to conserve power. The apparatus includes a target module coupled to a power and clock control module (PCCM). The PCCM sends an idleack signal to the target module when at least one initiator module within the device is in a power saving mode. When the target module satisfies conditions for idle mode, the target module sends an idleack signal to the PCCM and enters idle mode. In this state, the target module may process information but may not interact with other modules. When the target module detects a wakeup event, a wakeup signal is sent to the PCCM. When the PCCM returns the normal power and clock signal to the target module, the target module may resume normal operation.
摘要翻译：一种用于控制电子设备中的空闲模式的装置和方法。在空闲模式下，电源和时钟信号被减少或停止以节省电力。该装置包括耦合到电源和时钟控制模块（PCCM）的目标模块。当设备中的至少一个启动器模块处于省电模式时，PCCM向目标模块发送空闲信号。当目标模块满足空闲模式的条件时，目标模块向PCCM发送空闲信号并进入空闲模式。在这种状态下，目标模块可以处理信息，但可能不与其他模块交互。当目标模块检测到唤醒事件时，会向PCCM发送唤醒信号。当PCCM向目标模块返回正常的电源和时钟信号时，目标模块可以恢复正常运行。

3. 发明申请

US20070130383A1 Memory Information Transfer Power Management 有权
标题翻译：内存信息传输电源管理
公开(公告)号：US20070130383A1
公开(公告)日：2007-06-07
申请号：US11383416
申请日：2006-05-15
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost
IPC分类号： G06F13/28
CPC分类号： G06F1/3228 , G06F1/3215 , G06F1/3237 , G06F1/324 , G06F1/325 , G06F1/3275 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller coupled to a memory storage device and a peripheral device. The DMA controller transfers information from the memory storage device to a buffer in the peripheral device. The DMA controller may also transfer information from the buffer in the peripheral device to the memory storage device. When the peripheral device buffer does not have to be filled or emptied by the DMA controller, the DMA controller enters a standby mode. When the peripheral device buffer is full or empty, the DMA controller exits standby mode, empties or fills the peripheral device buffer, and reenters standby mode.
摘要翻译：一种用于在存储器信息传送系统中节省功率的装置和方法。该系统可以包括耦合到存储器存储设备和外围设备的直接存储器访问（DMA）控制器。 DMA控制器将信息从存储器存储设备传送到外围设备中的缓冲器。 DMA控制器还可以将信息从外围设备中的缓冲器传送到存储器存储设备。当外部设备缓冲区不需要由DMA控制器填充或清空时，DMA控制器进入待机模式。当外围设备缓冲区已满或空时，DMA控制器退出待机模式，清空或填充外围设备缓冲区，并重新进入待机模式。

4. 发明申请

US20070113111A1 Standby Mode for Power Management 有权
标题翻译：电源管理待机模式
公开(公告)号：US20070113111A1
公开(公告)日：2007-05-17
申请号：US11559388
申请日：2006-11-13
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost
IPC分类号： G06F1/00
CPC分类号： G06F1/3237 , G06F1/3228 , Y02D10/128 , Y02D50/20
摘要： An apparatus and method for controlling standby mode in an electronic device. In standby mode, power and clock signals are reduced or stopped to conserve power. The apparatus includes an initiator module coupled to a power and clock control module (PCCM). When the initiator module meets conditions for standby mode, the initiator module sends a standby signal to the PCCM and does not interact with other initiator, target, or interconnect modules. When the PCCM communicates a wait signal, the initiator module enters standby mode. When the initiator module detects a wakeup event, the standby signal is deactivated. In this state, the initiator module may process information but may not interact with other modules. When the PCCM deactivates the wait signal and returns power and clock signal to steady state levels, initiator module may resume normal operation.
摘要翻译：一种用于控制电子设备中的待机模式的装置和方法。在待机模式下，电源和时钟信号被减少或停止以节省电力。该装置包括耦合到电源和时钟控制模块（PCCM）的启动器模块。当启动器模块满足待机模式条件时，启动器模块向PCCM发送备用信号，不与其他启动器，目标或互连模块进行交互。当PCCM通信等待信号时，启动器模块进入待机模式。当启动器模块检测到唤醒事件时，待机信号被禁用。在这种状态下，启动器模块可以处理信息，但是可能不与其他模块进行交互。当PCCM关闭等待信号并将电源和时钟信号恢复到稳定状态时，启动器模块可以恢复正常工作。

5. 发明授权

US07840827B2 Display power management 有权
标题翻译：显示电源管理
公开(公告)号：US07840827B2
公开(公告)日：2010-11-23
申请号：US11559386
申请日：2006-11-13
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost , Jean Noel
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost , Jean Noel
IPC分类号： G06F1/32
CPC分类号： G09G5/363 , G09G5/18 , G09G5/39 , G09G2330/021
摘要： An apparatus and method for power management of a display system. A display controller couples to a memory storage device. A frame buffer in the memory storage device is filled with frames of information for display on a display device. The frames of information transfer to a display buffer in the display controller. The display controller transmits the frames of information from the display buffer to the display device. When frame information is not being transferred to the display controller, the display controller and the memory storage device may separately enter a power saving state. In power saving state, the display controller may continue to transmit frame information to the display device; however, power and a clock signal to components of display controller may be limited. When the display buffer is almost empty, the display controller exits power saving state to fill the display buffer.
摘要翻译：一种用于显示系统的电源管理的装置和方法。显示控制器耦合到存储器存储设备。存储器存储设备中的帧缓冲器被填充有用于在显示设备上显示的信息帧。信息帧传送到显示控制器中的显示缓冲器。显示控制器将信息帧从显示缓冲器发送到显示装置。当帧信息未被传送到显示控制器时，显示控制器和存储器存储设备可以分别进入省电状态。在省电状态下，显示控制器可以继续向显示装置发送帧信息; 然而，对显示控制器的组件的功率和时钟信号可能受到限制。当显示缓冲区几乎为空时，显示控制器退出省电状态以填充显示缓冲区。

6. 发明授权

US07587525B2 Power control with standby, wait, idle, and wakeup signals 有权
标题翻译：具有待机，等待，空闲和唤醒信号的电源控制
公开(公告)号：US07587525B2
公开(公告)日：2009-09-08
申请号：US11383416
申请日：2006-05-15
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost
IPC分类号： G06F13/28 , G06F1/26
CPC分类号： G06F1/3228 , G06F1/3215 , G06F1/3237 , G06F1/324 , G06F1/325 , G06F1/3275 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller coupled to a memory storage device and a peripheral device. The DMA controller transfers information from the memory storage device to a buffer in the peripheral device. The DMA controller may also transfer information from the buffer in the peripheral device to the memory storage device. When the peripheral device buffer does not have to be filled or emptied by the DMA controller, the DMA controller enters a standby mode. When the peripheral device buffer is full or empty, the DMA controller exits standby mode, empties or fills the peripheral device buffer, and reenters standby mode.
摘要翻译：一种用于在存储器信息传送系统中节省功率的装置和方法。该系统可以包括耦合到存储器存储设备和外围设备的直接存储器访问（DMA）控制器。 DMA控制器将信息从存储器存储设备传送到外围设备中的缓冲器。 DMA控制器还可以将信息从外围设备中的缓冲器传送到存储器存储设备。当外部设备缓冲区不需要由DMA控制器填充或清空时，DMA控制器进入待机模式。当外围设备缓冲区已满或空时，DMA控制器退出待机模式，清空或填充外围设备缓冲区，并重新进入待机模式。

7. 发明申请

US20070109292A1 Display Power Management 有权
标题翻译：显示电源管理
公开(公告)号：US20070109292A1
公开(公告)日：2007-05-17
申请号：US11559386
申请日：2006-11-13
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost , Jean Noel
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost , Jean Noel
IPC分类号： G09G5/00
CPC分类号： G09G5/363 , G09G5/18 , G09G5/39 , G09G2330/021
摘要： An apparatus and method for power management of a display system. A display controller couples to a memory storage device. A frame buffer in the memory storage device is filled with frames of information for display on a display device. The frames of information transfer to a display buffer in the display controller. The display controller transmits the frames of information from the display buffer to the display device. When frame information is not being transferred to the display controller, the display controller and the memory storage device may separately enter a power saving state. In power saving state, the display controller may continue to transmit frame information to the display device; however, power and a clock signal to components of display controller may be limited. When the display buffer is almost empty, the display controller exits power saving state to fill the display buffer.
摘要翻译：一种用于显示系统的电源管理的装置和方法。显示控制器耦合到存储器存储设备。存储器存储设备中的帧缓冲器被填充有用于在显示设备上显示的信息帧。信息帧传送到显示控制器中的显示缓冲器。显示控制器将信息帧从显示缓冲器发送到显示装置。当帧信息未被传送到显示控制器时，显示控制器和存储器存储设备可以分别进入省电状态。在省电状态下，显示控制器可以继续向显示装置发送帧信息; 然而，对显示控制器的组件的功率和时钟信号可能受到限制。当显示缓冲区几乎为空时，显示控制器退出省电状态以填充显示缓冲区。

8. 发明授权

US07737986B2 Methods and systems for tiling video or still image data 有权
标题翻译：用于平铺视频或静态图像数据的方法和系统
公开(公告)号：US07737986B2
公开(公告)日：2010-06-15
申请号：US11617820
申请日：2006-12-29
申请人： Franck Seigneret , Sylvain Dubois , Jean Pierre Noel , Pierre-Yves J. Taloud
发明人： Franck Seigneret , Sylvain Dubois , Jean Pierre Noel , Pierre-Yves J. Taloud
IPC分类号： G06F12/10 , G06F12/00 , G06F9/26 , G06F9/34 , G06G5/399
CPC分类号： G09G5/39 , G09G2360/122
摘要： The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing data that includes partitioning a display of graphical data into a plurality of two-dimensional tiles; mapping a two-dimensional tile of the plurality of two-dimensional tiles to a single memory row within a memory; and maintaining the graphical data for the two-dimensional tile in the single memory row.
摘要翻译：本公开描述了用于平铺视频或静止图像数据的方法和系统。至少一些优选实施例包括用于访问数据的方法，包括将图形数据的显示分割成多个二维瓦片; 将所述多个二维瓦片中的二维瓦片映射到存储器内的单个存储器行; 并且在单个存储器行中维护二维瓦片的图形数据。

9. 发明申请

US20080055325A1 METHODS AND SYSTEMS FOR TILING VIDEO OR STILL IMAGE DATA 有权
标题翻译：用于倾斜视频或静止图像数据的方法和系统
公开(公告)号：US20080055325A1
公开(公告)日：2008-03-06
申请号：US11617820
申请日：2006-12-29
申请人： Franck Seigneret , Sylvain Dubois , Jean Pierre Noel , Pierre-Yves J. Taloud
发明人： Franck Seigneret , Sylvain Dubois , Jean Pierre Noel , Pierre-Yves J. Taloud
IPC分类号： G06F13/00 , G09G5/39
CPC分类号： G09G5/39 , G09G2360/122
摘要： The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing data that includes partitioning a display of graphical data into a plurality of two-dimensional tiles; mapping a two-dimensional tile of the plurality of two-dimensional tiles to a single memory row within a memory; and maintaining the graphical data for the two-dimensional tile in the single memory row.
摘要翻译：本公开描述了用于平铺视频或静止图像数据的方法和系统。至少一些优选实施例包括用于访问数据的方法，包括将图形数据的显示分割成多个二维瓦片; 将所述多个二维瓦片中的二维瓦片映射到存储器内的单个存储器行; 并且在单个存储器行中维护二维瓦片的图形数据。

10. 发明授权

US06970207B1 Anti-flicker filtering process and system 有权
标题翻译：防闪烁过滤和系统
公开(公告)号：US06970207B1
公开(公告)日：2005-11-29
申请号：US09644957
申请日：2000-08-23
申请人： Franck Seigneret , Philippe Monnier , Emmanuel Chiaruzzi
发明人： Franck Seigneret , Philippe Monnier , Emmanuel Chiaruzzi
IPC分类号： H04N5/44 , H04N5/21
CPC分类号： H04N7/0132
摘要： A process of filtering digital images to reduce image flicker. An anti-flicker filtering is performed after a step of calculating the image and before a step of displaying the image so that the flicker is filtered as soon as the image is created.
摘要翻译：过滤数字图像以减少图像闪烁的过程。在计算图像的步骤之后和在显示图像的步骤之前执行防闪烁滤波，使得一旦创建图像，则闪烁被滤波。

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