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1. 发明授权

US08391052B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08391052B2
公开(公告)日：2013-03-05
申请号：US13043736
申请日：2011-03-09
申请人： Fumihiro Kono
发明人： Fumihiro Kono
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0016 , G11C13/0061 , G11C13/0069 , G11C2013/0066 , G11C2013/0076 , G11C2013/0083 , G11C2013/0092 , H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/147
摘要： A nonvolatile semiconductor memory device includes a memory cell array, the memory cell array including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of electrically rewritable memory cells disposed at each of intersections of the first lines and the second lines, each of the memory cells being configured from a variable resistor operative to store a resistance value of the variable resistor as data in a nonvolatile manner. A voltage supply circuit applies a certain voltage to the memory cells via the first lines and the second lines during writing data to the memory cells or forming of the memory cells. A detection circuit detects a change of the resistance value of the variable resistor in the memory cell during application of the certain voltage to the memory cells and outputs the detected change of the resistance value of the variable resistor as detection information. An output circuit outputs to external at least a portion of the detection information outputted from the detection circuit.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，所述存储单元阵列包括多个第一线，多条第二线与所述第一线相交，以及多个电可重写存储单元，设置在所述第一线的每个交点处线路和第二线路，每个存储器单元由可变电阻器构成，可变电阻器用于以非易失性方式存储可变电阻器的电阻值作为数据。电压电路在将数据写入存储单元或形成存储单元时，经由第一线和第二线向存储单元施加一定电压。检测电路检测在向存储单元施加一定电压期间存储单元中的可变电阻器的电阻值的变化，并输出检测到的可变电阻器的电阻值的变化作为检测信息。输出电路向外部输出从检测电路输出的检测信息的至少一部分。

2. 发明授权

US08144500B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08144500B2
公开(公告)日：2012-03-27
申请号：US12876746
申请日：2010-09-07
申请人： Fumihiro Kono
发明人： Fumihiro Kono
IPC分类号： G11C11/00
CPC分类号： G11C5/00 , G11C5/063 , G11C8/08
摘要： According to one embodiment, semiconductor memory device includes: semiconductor substrate; parallel first lines stacked on substrate; parallel second lines intersecting first lines; memory cell array including memory cells at intersections of first and second lines and each including variable resistance element and selecting element series-connected together; first control circuit provided in second region of substrate adjoining first region immediately under array; second control circuit provided in first region of substrate; and dummy lines formed in same layer as second lines, such that they intersect first lines in region above first control circuit. First control circuit applies first voltage to selected first line. Second control circuit applies second voltage lower than first voltage to selected second line, and to dummy lines, third voltage by which potential difference applied to memory cells at intersections of selected first line and dummy lines becomes lower than on-voltage of selecting element.
摘要翻译：根据一个实施例，半导体存储器件包括：半导体衬底; 平行的第一行堆叠在基板上; 平行的第二行与第一行相交; 存储单元阵列，包括在第一和第二行的交点处的存储单元，并且每个存储单元包括串联连接的可变电阻元件和选择元件; 第一控制电路，设置在邻近阵列下方的第一区域的基板的第二区域中; 第二控制电路，设置在基板的第一区域中; 以及与第二线相同的层形成的虚拟线，使得它们与第一控制电路上方的区域中的第一条线相交。第一控制电路将第一电压施加到所选择的第一行。第二控制电路对选择的第二线路施加低于第一电压的第二电压，对虚拟线路施加施加到所选择的第一线路和虚拟线路的交点处的存储器单元的电位差的第三电压变得低于选择元件的导通电压。

3. 发明申请

US20100027357A1 Memory System Having Distributed Read Access Delays 有权
标题翻译：具有分布式读访问延迟的内存系统
公开(公告)号：US20100027357A1
公开(公告)日：2010-02-04
申请号：US12183248
申请日：2008-07-31
申请人： Fumihiro Kono
发明人： Fumihiro Kono
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/18 , G11C11/413
摘要： A system having a plurality of memory cells organized in rows and columns. Each column includes upper and lower sets of memory cells connected to corresponding common upper/lower bit lines. Each column includes an evaluation circuit coupled to the upper and lower bit lines and configured to evaluate signals on these bit lines and to produce an output signal. Each of the upper and lower bit lines has an associated bit line delay, one of which is greater than the other. The evaluation circuit has first and second inputs which have associated evaluation delays, one of which is greater than the other. In each column, the bit line having the greater bit line delay is connected to the evaluation circuit input having the smaller evaluation delay, and the bit line having the smaller bit line delay is connected to the evaluation circuit input having the greater evaluation delay.
摘要翻译：具有以行和列组织的多个存储单元的系统。每列包括连接到相应的公共上/下位线的上下组的存储器单元。每列包括耦合到上位线和下位线的评估电路，并且被配置为评估这些位线上的信号并产生输出信号。上位线和下位线中的每一个具有相关联的位线延迟，其中一个延迟大于另一个。评估电路具有第一和第二输入，其具有相关联的评估延迟，其中一个大于另一个。在每列中，具有较大位线延迟的位线连接到具有较小评估延迟的评估电路输入，并且具有较小位线延迟的位线连接到具有较大评估延迟的评估电路输入。

4. 发明授权

US08873330B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08873330B2
公开(公告)日：2014-10-28
申请号：US13417503
申请日：2012-03-12
申请人： Fumihiro Kono , Kiyotaro Itagaki
发明人： Fumihiro Kono , Kiyotaro Itagaki
IPC分类号： G11C8/00 , G06F13/16 , G11C16/08 , G11C16/04
CPC分类号： G11C16/08 , G06F13/1694 , G11C16/0483
摘要： A plurality of address conversion circuits are provided for memory cores respectively, and convert logical address data supplied from outside to physical address data. In an interleave operation, the address conversion circuits output the logical address data as the physical address data without converting the logical address data when a first memory core is to be accessed earlier than a second memory core, whereas output address data obtained by adding a certain value to the logical address data as the physical address data when the second memory core is to be accessed earlier than the first memory core.
摘要翻译：分别为存储器核提供多个地址转换电路，并将从外部提供的逻辑地址数据转换为物理地址数据。在交错操作中，地址转换电路输出逻辑地址数据作为物理地址数据，而不需要在比第二存储器核心更先访问第一存储器核心时转换逻辑地址数据，而输出地址数据作为物理地址数据的逻辑地址数据的值作为第一存储器核心的第二存储器核心的存取时间。

5. 发明授权

US08804420B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08804420B2
公开(公告)日：2014-08-12
申请号：US13458218
申请日：2012-04-27
申请人： Fumihiro Kono
发明人： Fumihiro Kono
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/10 , G11C29/808
摘要： At least one of a plurality of columns is an LM column for storing LM flag data indicating a progression state of a write operation. Each of column control circuits performs an LM address scan operation for confirming whether the LM column exists in a corresponding memory core or not. Each of the column control circuits stores a result of that LM address scan operation in a register. In various kinds of operations after the LM address scan operation, each of the column control circuits executes an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is first data, and omits executing an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is second data.
摘要翻译：多列中的至少一列是用于存储指示写入操作的进行状态的LM标志数据的LM列。列控制电路中的每一个执行用于确认LM列是否存在于相应的存储器核心中的LM地址扫描操作。每个列控制电路将该LM地址扫描操作的结果存储在寄存器中。在LM地址扫描操作之后的各种操作中，每个列控制电路在保存在寄存器中的数据是第一数据时执行从相应的一个存储器核心中的LM列读取LM标志数据的操作，以及当保存在寄存器中的数据是第二数据时，省略从相应的一个存储器核心中的LM列读取LM标志数据的操作。

6. 发明授权

US07733717B2 Memory system having distributed read access delays 有权
标题翻译：具有分布式读取访问延迟的内存系统
公开(公告)号：US07733717B2
公开(公告)日：2010-06-08
申请号：US12183248
申请日：2008-07-31
申请人： Fumihiro Kono
发明人： Fumihiro Kono
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/18 , G11C11/413
摘要： A system having a plurality of memory cells organized in rows and columns. Each column includes upper and lower sets of memory cells connected to corresponding common upper/lower bit lines. Each column includes an evaluation circuit coupled to the upper and lower bit lines and configured to evaluate signals on these bit lines and to produce an output signal. Each of the upper and lower bit lines has an associated bit line delay, one of which is greater than the other. The evaluation circuit has first and second inputs which have associated evaluation delays, one of which is greater than the other. In each column, the bit line having the greater bit line delay is connected to the evaluation circuit input having the smaller evaluation delay, and the bit line having the smaller bit line delay is connected to the evaluation circuit input having the greater evaluation delay.
摘要翻译：具有以行和列组织的多个存储单元的系统。每列包括连接到相应的公共上/下位线的上下组的存储器单元。每列包括耦合到上位线和下位线的评估电路，并且被配置为评估这些位线上的信号并产生输出信号。上位线和下位线中的每一个具有相关联的位线延迟，其中一个延迟大于另一个。评估电路具有第一和第二输入，其具有相关联的评估延迟，其中一个大于另一个。在每列中，具有较大位线延迟的位线连接到具有较小评估延迟的评估电路输入，并且具有较小位线延迟的位线连接到具有较大评估延迟的评估电路输入。

7. 发明授权

US08817512B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08817512B2
公开(公告)日：2014-08-26
申请号：US13495366
申请日：2012-06-13
申请人： Fumihiro Kono
发明人： Fumihiro Kono
IPC分类号： G11C7/06 , G11C7/18 , G11C5/02
CPC分类号： G11C7/18 , G11C5/025 , G11C7/06
摘要： A semiconductor memory device comprises: a semiconductor substrate; a memory cell array provided above the semiconductor substrate and including a plurality of memory cells that are stacked; a plurality of bit lines connected electrically to the plurality of memory cells; and a plurality of sense amplifiers connected to the bit lines via bit line connection lines. The bit line connection lines have every adjacent N lines (where N is an integer of 2 or more) as one group. The sense amplifiers are arranged in a number smaller than N in a first direction that the bit line connection lines extend. An M number of the sense amplifiers are arranged in a width of a P number of groups in a second direction intersecting the first direction. The M number being larger than the P number.
摘要翻译：半导体存储器件包括：半导体衬底; 存储单元阵列，设置在所述半导体衬底上方，并且包括堆叠的多个存储单元; 多个与多个存储单元电连接的位线; 以及通过位线连接线连接到位线的多个读出放大器。位线连接线具有作为一组的每个相邻的N行（其中N是2或更大的整数）。读出放大器在位线连接线延伸的第一方向上以小于N的数量排列。 M个感测放大器在与第一方向相交的第二方向上以P个组的宽度布置。 M数大于P数。

8. 发明申请

US20130077401A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20130077401A1
公开(公告)日：2013-03-28
申请号：US13417503
申请日：2012-03-12
申请人： Fumihiro Kono , Kiyotaro Itagaki
发明人： Fumihiro Kono , Kiyotaro Itagaki
IPC分类号： G11C16/08
CPC分类号： G11C16/08 , G06F13/1694 , G11C16/0483
摘要： A plurality of address conversion circuits are provided for memory cores respectively, and convert logical address data supplied from outside to physical address data. In an interleave operation, the address conversion circuits output the logical address data as the physical address data without converting the logical address data when a first memory core is to be accessed earlier than a second memory core, whereas output address data obtained by adding a certain value to the logical address data as the physical address data when the second memory core is to be accessed earlier than the first memory core.
摘要翻译：分别为存储器核提供多个地址转换电路，并将从外部提供的逻辑地址数据转换为物理地址数据。在交错操作中，地址转换电路输出逻辑地址数据作为物理地址数据，而不需要在比第二存储器核心更先访问第一存储器核心时转换逻辑地址数据，而输出地址数据作为物理地址数据的逻辑地址数据的值作为第一存储器核心的第二存储器核心的存取时间。

9. 发明授权

US08406036B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08406036B2
公开(公告)日：2013-03-26
申请号：US13396710
申请日：2012-02-15
申请人： Fumihiro Kono
发明人： Fumihiro Kono
IPC分类号： G11C11/00
CPC分类号： G11C5/00 , G11C5/063 , G11C8/08
摘要： According to one embodiment, semiconductor memory device includes: semiconductor substrate; parallel first lines stacked on substrate; parallel second lines intersecting first lines; memory cell array including memory cells at intersections of first and second lines and each including variable resistance element and selecting element series-connected together; first control circuit provided in second region of substrate adjoining first region immediately under array; second control circuit provided in first region of substrate; and dummy lines formed in same layer as second lines, such that they intersect first lines in region above first control circuit. First control circuit applies first voltage to selected first line. Second control circuit applies second voltage lower than first voltage to selected second line, and to dummy lines, third voltage by which potential difference applied to memory cells at intersections of selected first line and dummy lines becomes lower than on-voltage of selecting element.
摘要翻译：根据一个实施例，半导体存储器件包括：半导体衬底; 平行的第一行堆叠在基板上; 平行的第二行与第一行相交; 存储单元阵列，包括在第一和第二行的交点处的存储单元，并且每个存储单元包括串联连接的可变电阻元件和选择元件; 第一控制电路，设置在邻近阵列下方的第一区域的基板的第二区域中; 第二控制电路，设置在基板的第一区域中; 以及与第二线相同的层形成的虚拟线，使得它们与第一控制电路上方的区域中的第一条线相交。第一控制电路将第一电压施加到所选择的第一行。第二控制电路对选择的第二线路施加低于第一电压的第二电压，对虚拟线路施加施加到所选择的第一线路和虚拟线路的交点处的存储器单元的电位差的第三电压变得低于选择元件的导通电压。

10. 发明授权

US08184501B2 Systems and methods for stretching clock cycles in the internal clock signal of a memory array macro 失效
标题翻译：用于在存储器阵列宏的内部时钟信号中拉伸时钟周期的系统和方法
公开(公告)号：US08184501B2
公开(公告)日：2012-05-22
申请号：US12475752
申请日：2009-06-01
申请人： Fumihiro Kono
发明人： Fumihiro Kono
IPC分类号： G11C8/00
CPC分类号： G11C8/18 , G11C7/1051 , G11C7/106 , G11C7/22 , G11C7/222
摘要： Systems and methods for stretching clock cycles of the internal clock signal of a memory array macro to allow more time for a data access in the macro than the period of an external clock signal. In one embodiment, a local clock buffer in the memory array macro receives a regular periodic external clock signal and generates an internal clock signal. The local clock buffer includes a first signal path that has one or more faster-than-nominal components so that the first rising edge of the internal clock cycle occurs early than it would in a clock buffer with nominal components. When the memory array macro is active for a data access, the local clock buffer stretches a clock cycle of the internal clock signal so that the first and second half-periods of the internal clock cycle are each greater than the half-periods of the external clock signal.
摘要翻译：用于延长存储器阵列宏的内部时钟信号的时钟周期的系统和方法，以允许在宏中的数据访问比外部时钟信号的周期更多的时间。在一个实施例中，存储器阵列宏中的本地时钟缓冲器接收规则的周期性外部时钟信号并产生内部时钟信号。本地时钟缓冲器包括具有一个或多个比标称分量更快的第一信号路径，使得内部时钟周期的第一上升沿比具有标称分量的时钟缓冲器中的时间早。当存储器阵列宏对数据访问有效时，本地时钟缓冲器延伸内部时钟信号的时钟周期，使得内部时钟周期的第一和第二半周期都大于外部时钟的半周期时钟信号。

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