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1. 发明申请

US20180189068A1 METHODS AND APPARATUS FOR ADJACENCY NETWORK DELIVERY OF OPERANDS TO INSTRUCTION SPECIFIED DESTINATIONS THAT REDUCES STORAGE OF TEMPORARY VARIABLES 审中-公开
公开(公告)号：US20180189068A1
公开(公告)日：2018-07-05
申请号：US15910211
申请日：2018-03-02
申请人： Gerald George Pechanek
发明人： Gerald George Pechanek
IPC分类号： G06F9/38 , G06F15/173 , G06F9/30
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/30181 , G06F9/3828 , G06F9/3836 , G06F9/3851 , G06F9/3895 , G06F15/17387
摘要： A system for pipelining signal flow graphs by a plurality of shared memory processors organized in a 3D physical arrangement with the memory overlaid on the processor nodes that reduces storage of temporary variables. A group function formed by two or more instructions to specify two or more parts of the group function. A first instruction specifies a first part and specifies control information for a second instruction adjacent to the first instruction or at a pre-specified location relative to the first instruction. The first instruction when executed transfers the control information to a pending register and produces a result which is transferred to an operand input associated with the second instruction. The second instruction specifies a second part of the group function and when executed transfers the control information from the pending register to a second execution unit to adjust the second execution unit's operation on the received operand.

2. 发明授权

US09672033B2 Methods and apparatus for transforming, loading, and executing super-set instructions 有权
公开(公告)号：US09672033B2
公开(公告)日：2017-06-06
申请号：US12350610
申请日：2009-01-08
申请人： Gerald George Pechanek , Larry D. Larsen
发明人： Gerald George Pechanek , Larry D. Larsen
IPC分类号： G06F15/00 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30047 , G06F9/30112 , G06F9/3013 , G06F9/30149 , G06F9/30174 , G06F9/382 , G06F9/3853 , G06F9/3885
摘要： Techniques are described for loading decoded instructions and super-set instructions in a memory for later access. For loading a decoded instruction, the decoded instruction is a transformed form of an original instruction that was stored in the program memory. The transformation is from an encoded assembly level format to a binary machine level format. In one technique, the transformation mechanism is invoked by a transform and load instruction that causes an instruction retrieved from program memory to be transformed into a new language format and then loaded into a transformed instruction memory. The format of the transformed instruction may be optimized to the implementation requirements, such as improving critical path timing. The transformation of instructions may extend to other needs beyond timing path improvement, for example, requiring super-set instructions for increased functionality and improvements to instruction level parallelism. Techniques for transforming, loading, and executing super-set instructions are described.

3. 发明授权

US08751772B2 Methods and apparatus for scalable array processor interrupt detection and response 失效
标题翻译：用于可扩展阵列处理器中断检测和响应的方法和装置
公开(公告)号：US08751772B2
公开(公告)日：2014-06-10
申请号：US13916877
申请日：2013-06-13
申请人： Edwin Franklin Barry , Patrick R. Marchand , Gerald George Pechanek , Larry D. Larsen
发明人： Edwin Franklin Barry , Patrick R. Marchand , Gerald George Pechanek , Larry D. Larsen
IPC分类号： G06F11/27
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debut monitor mechanism.
摘要翻译：描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。此外，使用分层中断结构，允许使用调试中断的通用调试方法和动态登场监视器机制。

4. 发明授权

US08489858B2 Methods and apparatus for scalable array processor interrupt detection and response 失效
标题翻译：用于可扩展阵列处理器中断检测和响应的方法和装置
公开(公告)号：US08489858B2
公开(公告)日：2013-07-16
申请号：US13417490
申请日：2012-03-12
申请人： Edwin Franklin Barry , Patrick R. Marchand , Gerald George Pechanek , Larry D. Larsen
发明人： Edwin Franklin Barry , Patrick R. Marchand , Gerald George Pechanek , Larry D. Larsen
IPC分类号： G06F15/00
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response are provided in a scalable pipelined array processor environment. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debug monitor mechanism.
摘要翻译：用于中断检测和响应的硬件和软件技术在可扩展的流水线阵列处理器环境中提供。利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。此外，使用分层中断结构，允许使用调试中断的通用调试方法和动态调试监视机制。

5. 发明授权

US08195732B2 Methods and apparatus for single stage Galois field operations 有权
标题翻译：单级Galois野外作业的方法和装置
公开(公告)号：US08195732B2
公开(公告)日：2012-06-05
申请号：US12265760
申请日：2008-11-06
申请人： Nikos P. Pitsianis , Gerald George Pechanek
发明人： Nikos P. Pitsianis , Gerald George Pechanek
IPC分类号： G06F7/00
CPC分类号： G06F7/724
摘要： Techniques for single function stage Galois field (GF) computations are described. Such a single function stage GF multiplication technique may utilize only m-bits per internal logic stage, a savings of m−1 bits per logic stage that do not have to be accounted for as compared with a previous two function stage approach. Also, a common design GF multiplication cell is described that may be suitably used to construct an m-by-m GF multiplication array for the calculation of GF[2m]/g[x]. In addition, these techniques are further described in the context of packed data form computation, very long instruction word (VLIW) processing, and processing on multiple processing elements in parallel.
摘要翻译：描述了单功能阶段伽罗瓦域（GF）计算的技术。这样的单功能级GF乘法技术可以仅利用每个内部逻辑级的m位，与前两种功能级方法相比，不需要考虑每个逻辑级的m-1位的节省。此外，描述了可以适当地用于构造用于计算GF [2m] / g [x]的m×m GF乘法阵列的公共设计GF乘法单元。另外，在打包数据形式计算，非常长的指令字（VLIW）处理和并行处理多个处理元件的上下文中进一步描述了这些技术。

6. 发明申请

US20110213937A1 Methods and Apparatus for Address Translation Functions 有权
标题翻译：地址转换功能的方法与装置
公开(公告)号：US20110213937A1
公开(公告)日：2011-09-01
申请号：US13105050
申请日：2011-05-11
申请人： Edwin Franklin Barry , Gerald George Pechanek
发明人： Edwin Franklin Barry , Gerald George Pechanek
IPC分类号： G06F12/00
CPC分类号： G06F9/30036 , G06F9/30032 , G06F9/3004 , G06F12/0292
摘要： Techniques are described for efficient reordering of data and performing data exchanges within a register tile or memory, or in general, any device storing data that is accessible through a set of addressable locations. In one technique, an address translator is placed in the path of all or a selected set of address busses to a storage device to provide a programmable and selectable means of translating the storage device addresses. An effect of this translation is that the data stored in one pattern may be accessed and stored in another pattern or accessed, processed and stored in another pattern. The address translation operation may be carried out in a single cycle, does not involve the physical movement of data in swap operations, allows data to effectively be ordered more efficiently for algorithmic processing and therefore saves power. Address translation functions are shown to be useful for vector operations and a new type of storage unit using built in address translation functions is presented.
摘要翻译：描述了用于有效重新排序数据和在寄存器块或存储器内执行数据交换的技术，或者一般地，存储可通过一组可寻址位置访问的数据的任何设备。在一种技术中，将地址转换器放置在存储设备的所有或一组所选地址总线的路径中，以提供可编程和可选择的翻译存储设备地址的装置。这种翻译的效果是存储在一个模式中的数据可以被访问和存储在另一种模式中，或以其他模式进行访问，处理和存储。地址转换操作可以在单个周期中执行，不涉及交换操作中的数据的物理移动，从而可以更有效地对数据进行有效地排序以进行算法处理，从而节省功率。地址转换功能被显示为对矢量操作有用，并且提供了使用内置地址转换功能的新型存储单元。

7. 发明授权

US07953955B2 Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture 有权
公开(公告)号：US07953955B2
公开(公告)日：2011-05-31
申请号：US12967662
申请日：2010-12-14
申请人： Sergei Yurievich Larin , Gerald George Pechanek , Thomas M. Conte
发明人： Sergei Yurievich Larin , Gerald George Pechanek , Thomas M. Conte
IPC分类号： G06F12/00
CPC分类号： G06F9/30178 , G06F8/447 , G06F9/30156 , G06F9/30167
摘要： A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application. A hardware embodiment described herein allows application of the above mentioned high-entropy encoding technique in actual embedded processor using today's technology without posing significant strain on timing requirements.

8. 发明申请

US20100318775A1 Methods and Apparatus for Adapting Pipeline Stage Latency Based on Instruction Type 有权
标题翻译：基于指令类型适应流水线延迟的方法与装置
公开(公告)号：US20100318775A1
公开(公告)日：2010-12-16
申请号：US12861896
申请日：2010-08-24
申请人： Edwin Franklin Barry , Gerald George Pechanek , Patrick R. Marchand
发明人： Edwin Franklin Barry , Gerald George Pechanek , Patrick R. Marchand
IPC分类号： G06F9/38
CPC分类号： G06F9/30079 , G06F9/30145 , G06F9/3869 , G06F9/3885
摘要： Processor pipeline controlling techniques are described which take advantage of the variation in critical path lengths of different instructions to achieve increased performance. By examining a processor's instruction set and execution unit implementation's critical timing paths, instructions are classified into speed classes. Based on these speed classes, one pipeline is presented where hold signals are used to dynamically control the pipeline based on the instruction class in execution. An alternative pipeline supporting multiple classes of instructions is presented where the pipeline clocking is dynamically changed as a result of decoded instruction class signals. A single pass synthesis methodology for multi-class execution stage logic is also described. For dynamic class variable pipeline processors, the mix of instructions can have a great effect on processor performance and power utilization since both can vary by the program mix of instruction classes. Application code can be given new degrees of optimization freedom where instruction class and the mix of instructions can be chosen based on performance and power requirements.
摘要翻译：描述了处理器流水线控制技术，其利用不同指令的关键路径长度的变化来实现增加的性能。通过检查处理器的指令集和执行单元实现的关键时序路径，指令被分为速度等级。基于这些速度等级，提出了一个管道，其中使用保持信号来基于执行中的指令类来动态地控制流水线。提出了支持多类指令的替代流水线，其中流水线时钟作为解码指令类信号的结果动态地改变。还描述了用于多类执行级逻辑的单程合成方法。对于动态类变量流水线处理器，指令的混合可以对处理器性能和功率利用率产生很大的影响，因为它们可以根据指令类的程序组合而变化。应用代码可以给出新的优化自由度，其中可以基于性能和功率要求来选择指令类和指令混合。

9. 再颁专利

USRE41703E1 Methods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communication 有权
标题翻译：用于IVLIW PE-TO-PE通信的高效同步MIMD操作的方法和装置
公开(公告)号：USRE41703E1
公开(公告)日：2010-09-14
申请号：US10872995
申请日：2004-06-21
申请人： Gerald George Pechanek , Thomas L. Drabenstott , Juan Guillermo Revilla , David Strube , Grayson Morris
发明人： Gerald George Pechanek , Thomas L. Drabenstott , Juan Guillermo Revilla , David Strube , Grayson Morris
IPC分类号： G06F15/16
CPC分类号： G06F9/30145 , G06F9/30167 , G06F9/3802 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization. Consequently, the term Synchronous-MIMD (SMIMD) is used to describe the present approach.
摘要翻译：使用多个并行处理器（PE）的SIMD机器，其中以有效的方式消除通信危险。使用间接超长指令字指令存储器（VIM）以及执行和分隔符指令。可以使用掩蔽机制来控制哪些PE装载有VIM。此外，优选采用操作的接收模式。在一个方面，每个PE操作以控制从其接收的PE选择的交换机。本发明解决了用于执行并行算法的更好的机器组织，其降低硬件成本和复杂性，同时保持SIMD和MIMD机器的最佳特性并最小化通信延迟。本发明为SIMD间接超长指令字（iVLIW）处理元件提供了MIMD计算自主性水平，同时保持了SIMD机器组织中使用的单一线程控制。因此，术语Synchronous-MIMD（SMIMD）用于描述当前的方法。

10. 发明申请

US20090276576A1 Methods and Apparatus storing expanded width instructions in a VLIW memory for deferred execution 有权
标题翻译：在VLIW存储器中存储用于延迟执行的扩展宽度指令的方法和装置
公开(公告)号：US20090276576A1
公开(公告)日：2009-11-05
申请号：US12499875
申请日：2009-07-09
申请人： Gerald George Pechanek , Stamatis Vassiliadis
发明人： Gerald George Pechanek , Stamatis Vassiliadis
IPC分类号： G06F9/30 , G06F12/00
CPC分类号： G06F9/38 , G06F9/3802
摘要： Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution arc addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.
摘要翻译：描述了用于将存储在主程序存储器中的指令的取出与指令的最早执行解耦的技术。解决支持这种执行的间接执行方法和程序指令。此外，描述了一种改进的间接延迟执行处理器（DXP）VLIW架构，其支持不需要本地加载和存储单元的可扩展阵列的存储器中心处理器元件。

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