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    • 2. 发明授权
    • Random seed stability with fuses
    • 保险丝随机种子稳定
    • US08165291B2
    • 2012-04-24
    • US11466867
    • 2006-08-24
    • Gerald L. ShipleyDavid A. Castaneda
    • Gerald L. ShipleyDavid A. Castaneda
    • H04L9/00
    • G01R31/2894
    • A circuit for stabilizing soft bits in a bit stream, the circuit having a first register to receive an initial read of the bit stream, a second register to receive a subsequent read of the bit stream, a comparator to compare the initial read of the bit stream to the subsequent read of the bit stream, a third register to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and an accumulator to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads.
    • 一种用于稳定比特流中的软比特的电路,该电路具有用于接收比特流的初始读取的第一寄存器,用于接收比特流的后续读取的第二寄存器,用于比较比特流的初始读取的比较器 流到后续读取比特流,第三寄存器用于接收比特串,其中比特串具有比特流的初始读取和比特流的后续读取不匹配的位置,指示位置中的软比特 以及累加器,用于接收用于比特流的多个后续读取的比较串,以及跟踪在多个后续读取期间检测到的所有软比特的位置。
    • 3. 发明申请
    • Random Seed Stability with Fuses
    • 随机种子与保险丝的稳定性
    • US20080068003A1
    • 2008-03-20
    • US11466867
    • 2006-08-24
    • Gerald L. ShipleyDavid A. Castaneda
    • Gerald L. ShipleyDavid A. Castaneda
    • G01R11/57
    • G01R31/2894
    • A circuit for stabilizing soft bits in a bit stream, the circuit having a first register to receive an initial read of the bit stream, a second register to receive a subsequent read of the bit stream, a comparator to compare the initial read of the bit stream to the subsequent read of the bit stream, a third register to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and an accumulator to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads.
    • 一种用于稳定比特流中的软比特的电路,该电路具有用于接收比特流的初始读取的第一寄存器,用于接收比特流的后续读取的第二寄存器,用于比较比特流的初始读取的比较器 流到后续读取比特流,第三寄存器用于接收比特串,其中比特串具有比特流的初始读取和比特流的后续读取不匹配的位置,指示位置中的软比特 以及累加器,用于接收用于比特流的多个后续读取的比较串,以及跟踪在多个后续读取期间检测到的所有软比特的位置。