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1. 发明申请

US20120105128A1 CALIBRATION OF PASSIVE HARMONIC-REJECTION MIXER 有权
标题翻译：被动谐波抑制混合器的校准
公开(公告)号：US20120105128A1
公开(公告)日：2012-05-03
申请号：US13266744
申请日：2010-04-23
申请人： Dennis Jeurissen , Gerben Willem de Jong , Jan van Sinderen , Johannes Hubertus Antonius Brekelmans
发明人： Dennis Jeurissen , Gerben Willem de Jong , Jan van Sinderen , Johannes Hubertus Antonius Brekelmans
IPC分类号： G06G7/12
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/1491 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
摘要翻译：一种包括无源谐波抑制混频器（400）和校准电路（425）的电子设备。无源谐波抑制混频器具有连接到多个子混频器级（402）的输入（102），并且子混频器级连接到用于产生输出（104）的求和模块（406,408）。每个子混合级包括门控模块（414），放大器（416）和加权模块（418），门控模块在控制信号的控制下选择性地使输入信号或具有反相极性的输入信号。校准电路（425）适于将参考信号（430）输入到混频器的输入端，从混频器的输出接收输出信号（104），并设定权重（K1，K2，K3，K4）的加权模块以使输出信号匹配期望的输出信号。

2. 发明授权

US08660508B2 Calibration of passive harmonic-rejection mixer 有权
标题翻译：无源谐波抑制混频器校准
公开(公告)号：US08660508B2
公开(公告)日：2014-02-25
申请号：US13266744
申请日：2010-04-23
申请人： Dennis Jeurissen , Gerben Willem de Jong , Jan van Sinderen , Johannes Hubertus Antonius Brekelmans
发明人： Dennis Jeurissen , Gerben Willem de Jong , Jan van Sinderen , Johannes Hubertus Antonius Brekelmans
IPC分类号： H04B17/00
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/1491 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
摘要翻译：一种包括无源谐波抑制混频器（400）和校准电路（425）的电子设备。无源谐波抑制混频器具有连接到多个子混频器级（402）的输入（102），并且子混频器级连接到用于产生输出（104）的求和模块（406,408）。每个子混合级包括门控模块（414），放大器（416）和加权模块（418），门控模块在控制信号的控制下选择性地使输入信号或具有反相极性的输入信号。校准电路（425）适于将参考信号（430）输入到混频器的输入端，从混频器的输出接收输出信号（104），并设定权重（K1，K2，K3，K4）的加权模块以使输出信号匹配期望的输出信号。

3. 发明授权

US08138817B2 Passive harmonic-rejection mixer 有权
标题翻译：被动谐波抑制混频器
公开(公告)号：US08138817B2
公开(公告)日：2012-03-20
申请号：US12738297
申请日：2008-10-29
申请人： Johannes Hubertus Antonius Brekelmans , Gerben Willem De Jong , Rachid El Waffaoui , Dennis Jeurissen , Jan Van Sinderen , Simon W K Lee
发明人： Johannes Hubertus Antonius Brekelmans , Gerben Willem De Jong , Rachid El Waffaoui , Dennis Jeurissen , Jan Van Sinderen , Simon W K Lee
IPC分类号： G06G7/12
CPC分类号： H03D7/165 , H03D7/18 , H03D2200/0082 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.
摘要翻译：一种包括无源谐波抑制混频器的电子设备。无源谐波抑制混频器具有连接到多个子混频器级的输入，并且子混频器级连接到用于产生输出的求和模块。每个子混合级包括门控模块和相应的放大器，门控模块适于在控制信号的控制下选择性地传递具有反相极性的输入信号或输入信号。

4. 发明授权

US07313060B2 Optical disk system with non-linearly controlled amplifier 失效
标题翻译：具有非线性控制放大器的光盘系统
公开(公告)号：US07313060B2
公开(公告)日：2007-12-25
申请号：US10523386
申请日：2003-07-21
申请人： Johannes Otto Voorman , Gerben Willem De Jong , Johannes Hubertus Antonius Brekelmans
发明人： Johannes Otto Voorman , Gerben Willem De Jong , Johannes Hubertus Antonius Brekelmans
IPC分类号： G11B7/00
CPC分类号： G11B20/10027 , G11B7/005 , G11B20/10009 , G11B2020/1288 , G11B2220/2541
摘要： An optical disk system includes at least one photo detector connected with a variable gain amplifier, a slicer, and a generator which is in the feedback path between the slicer and amplifier. A differential time delay detector provides the output of the optical disk system. The generator is configured for controlling the amplifier non-linearly so that time constants of the control loop of the amplifier which depend upon the level of the input signals are compensated and the timing behavior of the control loop of the amplifier has a more continuous character. A capacitor forms part of an integrator for making the mean value of the output voltage signal of the slicer equal to zero.
摘要翻译：光盘系统包括与可变增益放大器，限幅器和发生器连接的至少一个光电检测器，该可变增益放大器，限幅器和发生器处于限幅器和放大器之间的反馈路径中。差分延时检测器提供光盘系统的输出。发生器被配置为非线性地控制放大器，使得取决于输入信号的电平的放大器的控制环路的时间常数被补偿，并且放大器的控制环路的定时特性具有更连续的特性。电容器形成积分器的一部分，用于使限幅器的输出电压信号的平均值等于零。

5. 发明授权

US07038434B1 Voltage regulator 失效
标题翻译：电压调节器
公开(公告)号：US07038434B1
公开(公告)日：2006-05-02
申请号：US10523730
申请日：2003-07-21
申请人： Johannes Hubertus Antonius Brekelmans , Gerben Willem De Jong
发明人： Johannes Hubertus Antonius Brekelmans , Gerben Willem De Jong
IPC分类号： G05F1/40
CPC分类号： G05F1/575
摘要： A low dropout voltage regulator comprising a series-regulating element (T1) between an input (I) and an output (O) of the voltage regulator, and a differential input error amplifier (1) having a first output (O1) coupled to a control input of the series-regulating element (T1), characterized in that the error amplifier (1) further comprises a second output (O2) coupled to the output (O) via a high-pass filter (5, C1, R1).
摘要翻译：一种低压降稳压器，包括在电压调节器的输入（I）和输出（O）之间的串联调节元件（T 1）和差分输入误差放大器（1），其具有耦合的第一输出（O 1）到串联调节元件（T 1）的控制输入端，其特征在于误差放大器（1）还包括经由高通滤波器（5，C）耦合到输出端（O）的第二输出端（O 2） 1，R 1）。

6. 发明授权

US08203375B2 Frequency conversion 失效
标题翻译：变频
公开(公告)号：US08203375B2
公开(公告)日：2012-06-19
申请号：US12889259
申请日：2010-09-23
申请人： Gerben Willem de Jong , Johannes Hubertus Antonius Brekelmans
发明人： Gerben Willem de Jong , Johannes Hubertus Antonius Brekelmans
IPC分类号： G06F7/44 , G06G7/16
CPC分类号： H03D7/1441 , H03D7/1433 , H03D7/1458 , H03D7/1483 , H03D7/166 , H03D2200/0043 , H03D2200/0084
摘要： A frequency conversion circuit configured to mix a first input signal (RF+,RF−) at a first frequency with a second input signal (LO+,LO−) at a second frequency to provide an output intermediate frequency signal (IFout), the circuit comprising: first and second mixing modules, each mixing module comprising a voltage to current converter configured to receive the first input signal (RF+,RF−) and connected to a Gilbert mixer configured to receive the second input signal (LO+,LO−); an intermediate frequency output circuit having inputs connected to receive an intermediate frequency current signal (IF+,IF−) from outputs of each of the Gilbert mixers and an output configured to provide the output intermediate frequency voltage signal (IFout), wherein the first and second mixing modules comprise transistors which are complementary to each other.
摘要翻译：一种频率转换电路，被配置为将第一频率的第一输入信号（RF +，RF-）与第二频率的第二输入信号（LO +，LO-）混频以提供输出中频信号（IFout），所述电路包括：第一和第二混合模块，每个混合模块包括电压 - 电流转换器，配置成接收第一输入信号（RF +，RF-）并连接到配置成接收第二输入信号（LO +，LO-）的吉尔伯特混频器; 一个中频输出电路，具有输入端，用于接收来自Gilbert混合器每个输出端的中频电流信号（IF +，IF-）和被配置为提供输出中频电压信号（IFout）的输出端，其中第一和第二混合模块包括彼此互补的晶体管。

7. 发明授权

US07433292B2 Optical disk system with delay-difference detector without delay lines 失效
标题翻译：具有延迟差检测器的光盘系统，无延迟线
公开(公告)号：US07433292B2
公开(公告)日：2008-10-07
申请号：US10523385
申请日：2003-07-21
申请人： Johannes Otto Voorman , Gerben Willem De Jong , Johannes Hubertus Antonius Brekelmans
发明人： Johannes Otto Voorman , Gerben Willem De Jong , Johannes Hubertus Antonius Brekelmans
IPC分类号： G11B7/00
CPC分类号： G11B7/131 , G11B7/0901
摘要： Optical disk systems comprising photo detectors (1) for detecting optical disks comprising amplifiers and slicers (2-5) and delay-difference detectors (6) for detecting delay differences in sliced amplified detection signals are improved by installing delaylineless delay-difference detectors (6) comprising combinatorial-logic circuits (7,8) like inverters, ORs, NORs, ANDs, NANDs and sequential-logic circuits (11-18) like SetResetFlipFlops. Without the prior art delay lines, said delay-difference detectors (6) are of a lower complexity and low costly and can be well integrated. By introducing a first pair of sequential-logic circuits (11,12,15,16) for detecting delay differences between rising edges and a second pair of sequential-logic circuits (13,14,17,18) for detecting delay differences between falling edges, both kinds of edges are being used and the influence of time-jitter is less compared to the situation where just one kind of edge is used. Said delay-difference detector (6) further comprises an analog adder/subtracter (9) for adding/subtracting-logic circuit output signals and low pass filter(s) (10) located before or after said adder/subtracter (9).
摘要翻译：包括用于检测光盘的光检测器（1），包括用于检测分片放大检测信号中的延迟差的放大器和限幅器（2-5）和延迟差检测器（6），通过安装延迟无延迟差分检测器）包括类似反相器的组合逻辑电路（7,8），OR，NOR，AND，NAND和诸如SetResetFlipFlops的顺序逻辑电路（11-18）。在没有现有技术的延迟线的情况下，所述延迟差检测器（6）具有较低的复杂性并且成本低且可以很好地集成。通过引入用于检测上升沿之间的延迟差的第一对顺序逻辑电路（11,12,15,16）和用于检测下降沿之间的延迟差的第二对顺序逻辑电路（13,14,17,18）边缘，正在使用两种边缘，并且与仅使用一种边缘的情况相比，时间抖动的影响较小。所述延迟差检测器（6）还包括用于加/减逻辑电路输出信号的模拟加法器/减法器（9）和位于所述加法器/减法器（9）之前或之后的低通滤波器（10）。

8. 发明授权

US07170847B2 Means for limiting an output signal of an amplifier stage 失效
公开(公告)号：US07170847B2
公开(公告)日：2007-01-30
申请号：US10531012
申请日：2003-09-19
申请人： Gerben Willem De Jong , Johannes Hubertus Antonius Brekelmans , Jozef Reinerus Maria Bergervoet
发明人： Gerben Willem De Jong , Johannes Hubertus Antonius Brekelmans , Jozef Reinerus Maria Bergervoet
IPC分类号： G11B7/00
CPC分类号： H03F1/32 , G11B7/0053 , G11B7/1263 , G11B7/13 , H03F1/3211 , H03G7/06
摘要： An electronic circuit is provided which can autonomously handle an input current (Ii) having a relatively wide dynamic range without being overdriven. The electronic circuit comprises an amplifier stage (AMPST) having an input (IP) for receiving the input current (Ii) and an output (OP) for supplying an output current (Io), such that, during operation, the strength of the output current (Io) increases in response to an increasing strength of the input current (Ii) as long as the strength of the input current (Ii) has not exceeded an input reference level. The strength of the output current (Io) is kept approximately constant when the strength of the input current (Ii) has exceeded the input reference level but has not exceeded a further input reference level. The strength of the output current (Io) decreases in response to an increasing strength of the input current (Ii) when the strength of the input current (Ii) has exceeded the further input reference level. The amplifier stage (AMPST) may comprise a current mirror (CM) having an input which forms the input (IP), an output which forms the output (OP), and a common node (cn). The amplifier stage (AMPST) further comprises first control means (FCM) having an input connected to the input (EP), and an output connected to the common node (cn). First control means (FCM) controls a current (I2) to the common node (cn) and a voltage (Vcn) at the common node (cn). The first control means (FCM) comprises limiting means (LMT) for limiting the current (I2) when the value of the input current (Ii) has exceeded the input reference level. Then both the input and the output currents (Ii and Io) are limited. In order to avoid a saturation situation of a current source (Is) which supplies a current (I) to the input (EP), the amplifier stage (AMPST) may comprise second control means (SCM) for supplying a compensation current (ICMP) to the input (IP) when the input signal (Ii) has exceeded the input reference level. The current mirror (CM) comprises first (CP1) and second (CP2) current paths which form the core of the current mirror (CM), as is generally known. The decrease in response to an increasing strength of the input current (Ii) when the strength of the input current (Ii) has exceeded the further input reference level is implemented by a third current path (CP3) which takes away current from the second current path (CP2). Optionally, to avoid that the value of the output current (Io) can become too low, a fourth current path (CP4) may be implemented which applies current to the second current path (CP2). The inventive electronic circuit may be advantageously applied in all electronic systems (like CD-apparatus) which need means to limit a maximum output signal.

9. 发明授权

US07126385B2 Differential inverter circuit 有权
标题翻译：差分逆变电路
公开(公告)号：US07126385B2
公开(公告)日：2006-10-24
申请号：US10501427
申请日：2002-12-12
申请人： Johannes Hubertus Antonius Brekelmans , Josephus Arnoldus Henricus Maria Kahlman , Gerben Willem De Jong
发明人： Johannes Hubertus Antonius Brekelmans , Josephus Arnoldus Henricus Maria Kahlman , Gerben Willem De Jong
IPC分类号： H03K5/22
CPC分类号： H03F3/45179 , H03F3/3022 , H03F3/45748 , H03F3/45941 , H03F2203/30015 , H03F2203/45008 , H03F2203/45082 , H03F2203/45292 , H03F2203/45681
摘要： An improved differential inverter comprising a differential inverter having a differential input for receiving a first input signal and a second input signal, said inverter further comprising a differential control input for receiving a first control signal and a second control signal. The improved differential inverter further comprises a differential output for transmitting a first output signal and a second output signal. The improved differential inverter further comprises a controlled bias generator that generates the second vector of input signals in response to a bias control signal. The control bias signal is generated at an output of a voltage divider coupled to the differential output of the differential inverter said bias control signal being indicative for a DC voltage of the of the differential output.
摘要翻译：一种改进的差分逆变器，包括具有用于接收第一输入信号和第二输入信号的差分输入的差分反相器，所述反相器还包括用于接收第一控制信号和第二控制信号的差分控制输入。改进的差分逆变器还包括用于发送第一输出信号和第二输出信号的差分输出。改进的差分逆变器还包括受控偏置发生器，其响应于偏置控制信号产生输入信号的第二矢量。控制偏置信号在耦合到差分逆变器的差分输出的分压器的输出处产生，所述偏置控制信号指示差分输出的直流电压。

10. 发明授权

US09413407B2 Conversion system 有权
标题翻译：转换系统
公开(公告)号：US09413407B2
公开(公告)日：2016-08-09
申请号：US13178559
申请日：2011-07-08
申请人： Jan van Sinderen , Johannes Hubertus Antonius Brekelmans , Frank Harald Erich Ho Chung Leong , Nenad Pavlovic
发明人： Jan van Sinderen , Johannes Hubertus Antonius Brekelmans , Frank Harald Erich Ho Chung Leong , Nenad Pavlovic
IPC分类号： H03D3/22 , H04B1/30 , H03D7/16
CPC分类号： H04B1/30 , H03D7/16 , H03D7/165
摘要： The invention relates to frequency conversion systems, in particular for use as up-converters or down-converters in radiofrequency (RF) receivers or transmitters, exemplary embodiments including a radiofrequency receiver including an RF signal input; a mixing module including a first plurality of IF amplifiers each connected to the RF signal input via a switch; a multi-phase local oscillator signal generator configured to provide a switching signal to each switch; and a summing module configured to receive output signals from each of the IF amplifiers and to provide a second plurality of output IF signals from a weighted sum of the IF amplifier output signals, wherein the second plurality is different to the first plurality.
摘要翻译：本发明涉及频率转换系统，特别是用作射频（RF）接收机或发射机中的上转换器或下变频器，包括射频信号输入的射频接收机的示例性实施例; 混合模块，其包括经由开关连接到RF信号输入的第一多个IF放大器; 配置为向每个开关提供切换信号的多相本地振荡器信号发生器; 以及求和模块，被配置为从每个IF放大器接收输出信号，并且从IF放大器输出信号的加权和提供第二多个输出IF信号，其中第二多个不同于第一多个。

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