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1. 发明申请

US20120105128A1 CALIBRATION OF PASSIVE HARMONIC-REJECTION MIXER 有权
标题翻译：被动谐波抑制混合器的校准
公开(公告)号：US20120105128A1
公开(公告)日：2012-05-03
申请号：US13266744
申请日：2010-04-23
申请人： Dennis Jeurissen , Gerben Willem de Jong , Jan van Sinderen , Johannes Hubertus Antonius Brekelmans
发明人： Dennis Jeurissen , Gerben Willem de Jong , Jan van Sinderen , Johannes Hubertus Antonius Brekelmans
IPC分类号： G06G7/12
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/1491 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
摘要翻译：一种包括无源谐波抑制混频器（400）和校准电路（425）的电子设备。无源谐波抑制混频器具有连接到多个子混频器级（402）的输入（102），并且子混频器级连接到用于产生输出（104）的求和模块（406,408）。每个子混合级包括门控模块（414），放大器（416）和加权模块（418），门控模块在控制信号的控制下选择性地使输入信号或具有反相极性的输入信号。校准电路（425）适于将参考信号（430）输入到混频器的输入端，从混频器的输出接收输出信号（104），并设定权重（K1，K2，K3，K4）的加权模块以使输出信号匹配期望的输出信号。

2. 发明授权

US08660508B2 Calibration of passive harmonic-rejection mixer 有权
标题翻译：无源谐波抑制混频器校准
公开(公告)号：US08660508B2
公开(公告)日：2014-02-25
申请号：US13266744
申请日：2010-04-23
申请人： Dennis Jeurissen , Gerben Willem de Jong , Jan van Sinderen , Johannes Hubertus Antonius Brekelmans
发明人： Dennis Jeurissen , Gerben Willem de Jong , Jan van Sinderen , Johannes Hubertus Antonius Brekelmans
IPC分类号： H04B17/00
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/1491 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
摘要翻译：一种包括无源谐波抑制混频器（400）和校准电路（425）的电子设备。无源谐波抑制混频器具有连接到多个子混频器级（402）的输入（102），并且子混频器级连接到用于产生输出（104）的求和模块（406,408）。每个子混合级包括门控模块（414），放大器（416）和加权模块（418），门控模块在控制信号的控制下选择性地使输入信号或具有反相极性的输入信号。校准电路（425）适于将参考信号（430）输入到混频器的输入端，从混频器的输出接收输出信号（104），并设定权重（K1，K2，K3，K4）的加权模块以使输出信号匹配期望的输出信号。

3. 发明授权

US08638174B2 Digital signal generator 有权
标题翻译：数字信号发生器
公开(公告)号：US08638174B2
公开(公告)日：2014-01-28
申请号：US13116967
申请日：2011-05-26
申请人： Nenad Pavlovic , Johannes Hubertus Antonius Brekelmans , Jan van Sinderen
发明人： Nenad Pavlovic , Johannes Hubertus Antonius Brekelmans , Jan van Sinderen
IPC分类号： H03B27/00 , G06F1/04 , H04B1/10 , H04B1/16
CPC分类号： G06F1/025
摘要： The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and a plurality of input lines connected to respective output lines (203) of the bit sequence generator (201) and a clock signal input line (205), wherein the digital signal generator (202) is configured to provide an output bit sequence on the serial output line (204) at a rate given by a clock signal provided on the clock signal input line (205) and a sequence given by a sequence of bits from the bit sequence generator (201) on the plurality of input lines (203).
摘要翻译：本发明涉及用于提供用于数模转换器和谐波抑制混频器的本地振荡器信号的一个或多个相位的数字信号发生器。所公开的实施例包括用于射频接收机的混频器的本地振荡器信号发生器（200），所述信号发生器（200）包括具有多个并行输出线（203）的位序发生器（201），数字信号发生器）和连接到位序发生器（201）的相应输出线（203）的多条输入线和时钟信号输入线（205），其中数字信号发生器（202）是被配置为以由在时钟信号输入线（205）上提供的时钟信号给出的速率和由位序列发生器（201）的位序列给出的序列在串行输出线（204）上提供输出比特序列，在多个输入线（203）上。

4. 发明授权

US08138817B2 Passive harmonic-rejection mixer 有权
标题翻译：被动谐波抑制混频器
公开(公告)号：US08138817B2
公开(公告)日：2012-03-20
申请号：US12738297
申请日：2008-10-29
申请人： Johannes Hubertus Antonius Brekelmans , Gerben Willem De Jong , Rachid El Waffaoui , Dennis Jeurissen , Jan Van Sinderen , Simon W K Lee
发明人： Johannes Hubertus Antonius Brekelmans , Gerben Willem De Jong , Rachid El Waffaoui , Dennis Jeurissen , Jan Van Sinderen , Simon W K Lee
IPC分类号： G06G7/12
CPC分类号： H03D7/165 , H03D7/18 , H03D2200/0082 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.
摘要翻译：一种包括无源谐波抑制混频器的电子设备。无源谐波抑制混频器具有连接到多个子混频器级的输入，并且子混频器级连接到用于产生输出的求和模块。每个子混合级包括门控模块和相应的放大器，门控模块适于在控制信号的控制下选择性地传递具有反相极性的输入信号或输入信号。

5. 发明申请

US20110115539A1 SIGNAL PROCESSING ARRANGEMENT 有权
标题翻译：信号处理装置
公开(公告)号：US20110115539A1
公开(公告)日：2011-05-19
申请号：US13002818
申请日：2009-07-07
申请人： Johannes Hubertus Antonius Brekelmans
发明人： Johannes Hubertus Antonius Brekelmans
IPC分类号： H03H11/26
CPC分类号： H03K23/54
摘要： A signal processing arrangement comprises a series of latches (XDL, L1, L2) arranged as a clocked delay line (CDL) having a data input and a data output that are coupled to each other so as to form an inverting loop. An enable circuit (ACDL) allows or prevents a latch (L2) in the series of latches from changing state depending on whether, one clock cycle ago, the latch concerned received a given binary value or the inverse of that given binary 5 value, respectively, from the preceding latch (L1) in the series of latches. Such a circuit configuration allows a low-cost frequency division by an odd number with relatively small duty cycle errors.
摘要翻译：信号处理装置包括被布置为具有数据输入的时钟延迟线（CDL）的一系列锁存器（XDL，L1，L2）和彼此耦合以形成反相环路的数据输出。使能电路（ACDL）允许或防止一系列锁存器中的锁存器（L2）根据一个时钟周期之前的锁存器是否分别接收到给定的二进制值或者给定的二进制值5的反相来改变状态，从一系列闩锁中的先前锁存（L1）开始。这种电路配置允许以相对小的占空比误差的低成本分频奇数。

6. 发明授权

US07499694B1 Tuner alignment 有权
标题翻译：调谐器对齐
公开(公告)号：US07499694B1
公开(公告)日：2009-03-03
申请号：US09890490
申请日：2000-11-27
申请人： Alan Chin Leong Yeo , Han Leng Paxton Tan , Johannes Hubertus Antonius Brekelmans
发明人： Alan Chin Leong Yeo , Han Leng Paxton Tan , Johannes Hubertus Antonius Brekelmans
IPC分类号： H04B1/16 , H04B7/00
CPC分类号： H03J3/08 , H03J1/0033 , H04N5/50 , H04N21/4383 , H04N21/44209
摘要： In a method of tuning a receiver for a digital signal (MPEG2-TS), an input signal (RF-in) is filtered (In-filt, Band-filt) to obtain a processed signal, a digital figure of merit (BER) is determined (Mix/Osc/IF amp IF-downconv-2, C) from the processed signal, and the filtering step (In-filt, Band-filt) is fine-adjusted (μP, PLL, DAC1-DAC3) in dependence on the digital figure of merit (BER).
摘要翻译：在对数字信号（MPEG2-TS）的接收机进行调谐的方法中，对输入信号（RF-in）进行滤波（滤波，频带滤波）以获得经处理的信号，数字品质因数（BER）从处理信号中确定（Mix / Osc / IF amp IF-downconv-2，C），依次对滤波步骤（In-filt，Band-filt）进行微调（muP，PLL，DAC1-DAC3）关于数字品质因数（BER）。

7. 发明申请

US20090021332A1 ARRAY OF CAPACITORS SWITCHED BY MOS TRANSISTORS 审中-公开
标题翻译： MOS晶体管开关电容阵列
公开(公告)号：US20090021332A1
公开(公告)日：2009-01-22
申请号：US11576808
申请日：2005-10-05
申请人： Johannes Hubertus Antonius Brekelmans , Vincent Rambeau , Jan Van Sinderen , Marc Godfriedus Marie Notten
发明人： Johannes Hubertus Antonius Brekelmans , Vincent Rambeau , Jan Van Sinderen , Marc Godfriedus Marie Notten
IPC分类号： H03J5/24
CPC分类号： H01L27/0805 , H01L27/0629 , H03H7/25 , H03J2200/10
摘要： An integrated variable capacitance with low losses comprises an array (1) of switched capacitors (2-8). When using an array (1) of switched capacitors (2-8) to form a quasi continuously variable capacitor, a continuity of capacitance as function of the digital control signal to the array (1) leads to overall behavior of the series resistance of the array (1) as function of the capacitance that for some applications may be undesirable. Therefore a topology for a switched array (1) is proposed that allows to set series resistance relatively independent from capacitance. The array (1) may be fully or partially integrated in tunable LC filters, also in TV tuners.
摘要翻译：具有低损耗的集成可变电容包括开关电容器（2-8）的阵列（1）。当使用开关电容器（2〜8）的阵列（1〜8）形成准连续可变电容器时，作为阵列（1）的数字控制信号的功能的电容的连续性导致了串联电阻作为对于一些应用的电容的函数的数组（1）可能是不期望的。因此，提出了一种用于开关阵列（1）的拓扑，其允许相对独立于电容设置串联电阻。阵列（1）可以完全或部分地集成在可调LC滤波器中，也可以在电视调谐器中。

8. 发明授权

US07352235B2 Current mirror 有权
标题翻译：电流镜
公开(公告)号：US07352235B2
公开(公告)日：2008-04-01
申请号：US10548252
申请日：2004-03-01
申请人： Hugo Veenstra , Godefridus Adrianus Maria Hurkx , Johannes Hubertus Antonius Brekelmans , Dave Willem Van Goor
发明人： Hugo Veenstra , Godefridus Adrianus Maria Hurkx , Johannes Hubertus Antonius Brekelmans , Dave Willem Van Goor
IPC分类号： G05F1/10
CPC分类号： G05F3/265
摘要： The present invention relates to Current mirror for generating a constant mirror ratio, comprising an output transistor (Tout) having a base, an emitter and a collector, wherein a current flowing through the collector of said output transistor (Tout) constitutes an output current (Iout) of said current mirror and the collector of said output transistor (Tout) is connectable to an output circuit, a buffer transistor having a base, an emitter and a collector, wherein the emitter of the buffer transistor is connected to the base of the output transistor, a buffer current source for providing a fixed buffer current, wherein said buffer current source is connected to the collector of the buffer transistor, and a buffer base voltage control means having an input connected to the base of the output transistor and an output connected to the base of the buffer transistor, wherein the base voltage control means is adapted to controlling a voltage at the base of the buffer transistor in response to a current at the input of the buffer base voltage control means.
摘要翻译：本发明涉及用于产生恒定镜面比例的电流镜，其包括具有基极，发射极和集电极的输出晶体管（T OUT），其中流过所述输出的集电极的电流晶体管（T out out out）构成所述电流镜的输出电流（I OUT），并且所述输出晶体管的集电极（T out out）是可连接到输出电路，具有基极，发射极和集电极的缓冲晶体管，其中缓冲晶体管的发射极连接到输出晶体管的基极，缓冲电流源用于提供固定的缓冲电流，其中所述缓冲器电流源连接到缓冲晶体管的集电极，以及缓冲器基极电压控制装置，其具有连接到输出晶体管的基极的输入端和连接到缓冲晶体管的基极的输出，其中基极电压控制装置被适配以控制电压 e缓冲晶体管的基极，响应于缓冲器基极电压控制装置的输入处的电流。

9. 发明授权

US08354886B2 Arrangement for calibrating the quiescent operating point of a push-pull amplifier 有权
标题翻译：用于校准推挽放大器的静态工作点的布置
公开(公告)号：US08354886B2
公开(公告)日：2013-01-15
申请号：US13058276
申请日：2009-08-10
申请人： Johannes Hubertus Antonius Brekelmans
发明人： Johannes Hubertus Antonius Brekelmans
IPC分类号： H03F3/26
CPC分类号： H03F1/308 , H03F1/3217 , H03F3/3028 , H03F3/345 , H03F2203/30003 , H03F2203/30033
摘要： A signal processing arrangement comprises an amplifier (AMP V1) that includes a stage with complementary transistors (MP3, MN3) of opposite conductivity type arranged in series between two supply lines (+, −). A controllable biasing circuit (CCS) is provided for changing a quiescent operating point of the stage as a function of a control signal (CS). A control arrangement measures an even order 5 distortion of the amplifier (AMP V1) and adjusts the control signal (CS) so that the even order distortion is below a critical level.
摘要翻译：信号处理装置包括放大器（AMP V1），放大器（AMP V1）包括具有串联布置在两条电源线（+， - ）之间的相反导电类型的互补晶体管（MP3，MN3）的平台。提供了可控偏置电路（CCS），用于根据控制信号（CS）来改变级的静态工作点。控制装置测量放大器（AMP V1）的偶数阶失真5并调整控制信号（CS），使偶数阶失真低于临界水平。

10. 发明授权

US08135375B2 Receiver having a gain-controllable stage 有权
标题翻译：接收机具有增益可控级
公开(公告)号：US08135375B2
公开(公告)日：2012-03-13
申请号：US12065315
申请日：2006-08-23
申请人： Johannes Hubertus Antonius Brekelmans
发明人： Johannes Hubertus Antonius Brekelmans
IPC分类号： H04B1/16
CPC分类号： H03G3/3052
摘要： A gain-controllable stage (CLN, A1, A2 . . . , A7, ACC) comprises a reactive signal divider (CLN) followed by an amplifier arrangement (A1, A2 . . . , A7, ACC). The reactive signal divider (CLN) may be in the form of, for example, a capacitive ladder network. The gain-controllable stage (CLN, A1, A2 . . . , A7, ACC) has a gain factor that depends on a signal division factor that the reactive signal divider (CLN) provides. The reactive signal divider (CLN) forms part of a filter (LC). The signal division factor is adjusted on the basis of a frequency (F) to which the receiver is tuned and a signal-strength indication (RS).
摘要翻译：增益可控级（CLN，A1，A2 ...，A7，ACC）包括一个无功信号分频器（CLN），后面是一个放大器装置（A1，A2 ... A7，ACC）。无功信号分配器（CLN）可以是例如电容梯形网络的形式。增益可控级（CLN，A1，A2 ... A7，ACC）具有取决于无功信号分频器（CLN）提供的信号分配因子的增益因子。无功信号分频器（CLN）形成滤波器（LC）的一部分。基于接收机调谐的频率（F）和信号强度指示（RS）来调整信号分配因子。

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