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1. 发明申请

US20110095794A1 Enhancement of Power Management Using Dynamic Voltage and Frequency Scaling and Digital Phase Lock Loop High Speed Bypass Mode 有权
标题翻译：使用动态电压和频率缩放和数字锁相环高速旁路模式增强电源管理
公开(公告)号：US20110095794A1
公开(公告)日：2011-04-28
申请号：US12607981
申请日：2009-10-28
申请人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
发明人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , H03L7/0812 , H03L7/22
摘要： An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.
摘要翻译：一种用于时钟/电压缩放的装置包括：设备功率管理器，被布置为向接口提供可缩放的频率时钟; 由恒定的固定频率时钟和恒定电压提供的延迟锁定环路，被布置成根据过程，电压和/或温度产生唯一的代码; 以及耦合到所述延迟锁定环路的受控延迟线路元件，被布置为基于所述唯一码产生适当的延迟数据选通。一种用于数字锁相环高速旁路模式的方法包括在第一高速时钟域中提供第一数字锁相环; 在第二时钟域中提供第二数字锁相环; 使用本地同步的设备电源管理器根据预选设置来控制第一无毛刺多路复用器的输出; 以及使用所述第二数字锁相环的控制逻辑元件来控制第二无毛刺多路复用器的输出。

2. 发明授权

US08278980B1 Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode 有权
公开(公告)号：US08278980B1
公开(公告)日：2012-10-02
申请号：US13484472
申请日：2012-05-31
申请人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
发明人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , H03L7/0812 , H03L7/22
摘要： An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.

3. 发明申请

US20120235716A1 ENHANCEMENT OF POWER MANAGEMENT USING DYNAMIC VOLTAGE AND FREQUENCY SCALING AND DIGITAL PHASE LOCK LOOP HIGH SPEED BYPASS MODE 有权
标题翻译：使用动态电压和频率调节和数字相位锁定循环高速旁路模式进行电源管理的增强
公开(公告)号：US20120235716A1
公开(公告)日：2012-09-20
申请号：US13484472
申请日：2012-05-31
申请人： GILLES DUBOST , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
发明人： GILLES DUBOST , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
IPC分类号： H03L7/08
CPC分类号： H03L7/0805 , H03L7/0812 , H03L7/22
摘要： An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.
摘要翻译：一种用于时钟/电压缩放的装置包括：设备功率管理器，被布置为向接口提供可缩放的频率时钟; 由恒定的固定频率时钟和恒定电压提供的延迟锁定环路，被布置成根据过程，电压和/或温度产生唯一的代码; 以及耦合到所述延迟锁定环路的受控延迟线路元件，被布置为基于所述唯一码产生适当的延迟数据选通。一种用于数字锁相环高速旁路模式的方法包括在第一高速时钟域中提供第一数字锁相环; 在第二时钟域中提供第二数字锁相环; 使用本地同步的设备电源管理器根据预选设置来控制第一无毛刺多路复用器的输出; 以及使用所述第二数字锁相环的控制逻辑元件来控制第二无毛刺多路复用器的输出。

4. 发明授权

US08207764B2 Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode 有权
标题翻译：使用动态电压和频率缩放和数字锁相环高速旁路模式增强电源管理
公开(公告)号：US08207764B2
公开(公告)日：2012-06-26
申请号：US12607981
申请日：2009-10-28
申请人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
发明人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , H03L7/0812 , H03L7/22
摘要： An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.
摘要翻译：一种用于时钟/电压缩放的装置包括：设备功率管理器，被布置为向接口提供可缩放的频率时钟; 由恒定的固定频率时钟和恒定电压提供的延迟锁定环路，被布置成根据过程，电压和/或温度产生唯一的代码; 以及耦合到所述延迟锁定环路的受控延迟线路元件，被布置为基于所述唯一码产生适当的延迟数据选通。一种用于数字锁相环高速旁路模式的方法包括在第一高速时钟域中提供第一数字锁相环; 在第二时钟域中提供第二数字锁相环; 使用本地同步的设备电源管理器根据预选设置来控制第一无毛刺多路复用器的输出; 以及使用所述第二数字锁相环的控制逻辑元件来控制第二无毛刺多路复用器的输出。

5. 发明授权

US08458429B2 Memory controller idle mode 有权
标题翻译：内存控制器空闲模式
公开(公告)号：US08458429B2
公开(公告)日：2013-06-04
申请号：US11948844
申请日：2007-11-30
申请人： Franck Dahan , Gilles Dubost , Sylvain Dubois
发明人： Franck Dahan , Gilles Dubost , Sylvain Dubois
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F1/00 , G06F1/26 , G06F1/32 , G06F11/30 , G06F1/04 , G06F1/12 , G06F5/06
CPC分类号： G06F13/1694 , Y02D10/14
摘要： An apparatus and method for dynamically modifying one or more operating conditions of a memory controller in an electronic device. Operating conditions may comprise clock frequency and power, which may be modified or removed. Dynamic modification of operating conditions may be done for purposes of optimizing a parameter, such as power consumption. A mode, referred to as idle mode, may be used as a transitional or operational mode for the memory controller. The performance of the memory controller may dynamically vary in response to changes in its operating conditions. As such, the memory controller may comprise multiple modes, or submodes, of operation. The performance of the memory controller may depend on the type of memory it controls, for instance Double Data Rate (DDR) Dynamic Random Access Memory (DRAM).
摘要翻译：一种用于动态修改电子设备中的存储器控制器的一个或多个操作条件的装置和方法。操作条件可以包括时钟频率和功率，其可以被修改或去除。操作条件的动态修改可以用于优化诸如功率消耗之类的参数的目的。称为空闲模式的模式可以用作存储器控制器的过渡或操作模式。存储器控制器的性能可以根据其操作条件的变化而动态变化。因此，存储器控制器可以包括操作的多种模式或子模式。存储器控制器的性能可以取决于其控制的存储器的类型，例如双数据速率（DDR）动态随机存取存储器（DRAM）。

6. 发明申请

US20080162980A1 Memory Controller Idle Mode 有权
标题翻译：内存控制器空闲模式
公开(公告)号：US20080162980A1
公开(公告)日：2008-07-03
申请号：US11948844
申请日：2007-11-30
申请人： Franck Dahan , Gilles Dubost , Sylvain Dubois
发明人： Franck Dahan , Gilles Dubost , Sylvain Dubois
IPC分类号： G06F5/06 , G06F12/00
CPC分类号： G06F13/1694 , Y02D10/14
摘要： An apparatus and method for dynamically modifying one or more operating conditions of a memory controller in an electronic device. Operating conditions may comprise clock frequency and power, which may be modified or removed. Dynamic modification of operating conditions may be done for purposes of optimizing a parameter, such as power consumption. A mode, referred to as idle mode, may be used as a transitional or operational mode for the memory controller. The performance of the memory controller may dynamically vary in response to changes in its operating conditions. As such, the memory controller may comprise multiple modes, or submodes, of operation. The performance of the memory controller may depend on the type of memory it controls, for instance Double Data Rate (DDR) Dynamic Random Access Memory (DRAM).
摘要翻译：一种用于动态修改电子设备中的存储器控制器的一个或多个操作条件的装置和方法。操作条件可以包括时钟频率和功率，其可以被修改或去除。操作条件的动态修改可以用于优化诸如功率消耗之类的参数的目的。称为空闲模式的模式可以用作存储器控制器的过渡或操作模式。存储器控制器的性能可以根据其操作条件的变化而动态变化。因此，存储器控制器可以包括操作的多种模式或子模式。存储器控制器的性能可以取决于其控制的存储器的类型，例如双数据速率（DDR）动态随机存取存储器（DRAM）。

7. 发明申请

US20110224810A1 HOME AND BUILDING AUTOMATION 审中-公开
标题翻译：家居建筑自动化
公开(公告)号：US20110224810A1
公开(公告)日：2011-09-15
申请号：US12723590
申请日：2010-03-12
申请人： Sylvain Dubois , Joe Tom
发明人： Sylvain Dubois , Joe Tom
IPC分类号： G06F17/00
CPC分类号： G05B15/02 , G05B19/042 , G05B2219/23043 , G05B2219/23077 , G05B2219/2642
摘要： Systems (100) and methods (500) for controlling a household electronic device (HED). The HED (102, . . . , 114, 142) comprises a processing unit (302) configured to execute first device-control software operative for controlling the HED so that it performs a primary function using original values for a plurality of operating parameters. The methods involve receiving, at the HED, an active processing module (130, . . . , 140, 144, 146) configured to execute second device-control software. The second device-control software is operative for controlling the HED so that HED performs the primary function using a customized value for one or more of the operating parameters or performs a secondary function different than the primary function.
摘要翻译：用于控制家用电子设备（HED）的系统（100）和方法（500）。 HED（102，...，114,142）包括处理单元（302），其被配置为执行用于控制HED的第一设备控制软件，使得其使用多个操作参数的原始值来执行主要功能。所述方法包括在HED处接收被配置为执行第二设备控制软件的主动处理模块（130，...，140,144,146）。第二设备控制软件可操作用于控制HED，使得HED使用针对一个或多个操作参数的定制值来执行主要功能，或执行与主要功能不同的辅助功能。

8. 发明授权

US07737986B2 Methods and systems for tiling video or still image data 有权
标题翻译：用于平铺视频或静态图像数据的方法和系统
公开(公告)号：US07737986B2
公开(公告)日：2010-06-15
申请号：US11617820
申请日：2006-12-29
申请人： Franck Seigneret , Sylvain Dubois , Jean Pierre Noel , Pierre-Yves J. Taloud
发明人： Franck Seigneret , Sylvain Dubois , Jean Pierre Noel , Pierre-Yves J. Taloud
IPC分类号： G06F12/10 , G06F12/00 , G06F9/26 , G06F9/34 , G06G5/399
CPC分类号： G09G5/39 , G09G2360/122
摘要： The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing data that includes partitioning a display of graphical data into a plurality of two-dimensional tiles; mapping a two-dimensional tile of the plurality of two-dimensional tiles to a single memory row within a memory; and maintaining the graphical data for the two-dimensional tile in the single memory row.
摘要翻译：本公开描述了用于平铺视频或静止图像数据的方法和系统。至少一些优选实施例包括用于访问数据的方法，包括将图形数据的显示分割成多个二维瓦片; 将所述多个二维瓦片中的二维瓦片映射到存储器内的单个存储器行; 并且在单个存储器行中维护二维瓦片的图形数据。

9. 发明申请

US20080055325A1 METHODS AND SYSTEMS FOR TILING VIDEO OR STILL IMAGE DATA 有权
标题翻译：用于倾斜视频或静止图像数据的方法和系统
公开(公告)号：US20080055325A1
公开(公告)日：2008-03-06
申请号：US11617820
申请日：2006-12-29
申请人： Franck Seigneret , Sylvain Dubois , Jean Pierre Noel , Pierre-Yves J. Taloud
发明人： Franck Seigneret , Sylvain Dubois , Jean Pierre Noel , Pierre-Yves J. Taloud
IPC分类号： G06F13/00 , G09G5/39
CPC分类号： G09G5/39 , G09G2360/122
摘要： The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing data that includes partitioning a display of graphical data into a plurality of two-dimensional tiles; mapping a two-dimensional tile of the plurality of two-dimensional tiles to a single memory row within a memory; and maintaining the graphical data for the two-dimensional tile in the single memory row.
摘要翻译：本公开描述了用于平铺视频或静止图像数据的方法和系统。至少一些优选实施例包括用于访问数据的方法，包括将图形数据的显示分割成多个二维瓦片; 将所述多个二维瓦片中的二维瓦片映射到存储器内的单个存储器行; 并且在单个存储器行中维护二维瓦片的图形数据。

10. 发明授权

US6139638A Fluid assisted doctor 失效
标题翻译：流体辅助医生
公开(公告)号：US6139638A
公开(公告)日：2000-10-31
申请号：US229433
申请日：1999-01-13
申请人： Sylvain Dubois , Claude Mallette
发明人： Sylvain Dubois , Claude Mallette
IPC分类号： D21G3/00 , B05C1/04
CPC分类号： D21G3/005
摘要： A holder is disclosed for applying the working edge of a doctor blade to a moving surface. The holder has upper and lower holder members constructed and arranged respectively to contact upper and lower surfaces of the doctor blade, with the doctor blade projecting forwardly to terminate at its working edge. One of the holder members comprises a composite of sandwiched elements enclosing one or more chambers having forwardly directed outlets. A pressurized fluid is introduced into the chambers for forward application via the outlets and along a surface of said doctor blade onto the surface being doctored.
摘要翻译：公开了用于将刮刀的工作边缘施加到移动表面的保持器。保持器具有分别构造和分别布置成接触刮刀的上表面和下表面的上和下保持器构件，刮刀向前突出以终止于其工作边缘。保持器构件中的一个包括包围具有向前定向的出口的一个或多个室的夹层元件的复合物。加压流体被引入腔室中，用于经由出口以及沿着刮刀的表面正向施加到待被干燥的表面上。

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