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1. 发明授权

US07831039B2 AES encryption circuitry with CCM 有权
标题翻译：具有CCM的AES加密电路
公开(公告)号：US07831039B2
公开(公告)日：2010-11-09
申请号：US11448424
申请日：2006-06-07
申请人： Guido Bertoni , Jefferson E. Owen
发明人： Guido Bertoni , Jefferson E. Owen
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28 , H04L9/32
CPC分类号： H04L9/0631 , H04L9/0637 , H04L9/3242 , H04L2209/125 , H04L2209/24 , H04L2209/38 , H04L2209/80
摘要： Circuitry for encrypting at least a part of an input data flow and generating a tag based on the input data flow with the same ciphering algorithm and the same key including a first ciphering branch arranged to encrypt the at least part of the input data; a second ciphering branch arranged to generate the tag; and a single key schedule unit arranged to receive the key, to generate at least one sub-key based on the key and to provide the at least one sub-key to the first and second ciphering branches.
摘要翻译：电路，用于对输入数据流的至少一部分进行加密，并且以相同的加密算法和相同的密钥生成基于输入数据流的标签，该密钥包括布置成加密输入数据的至少部分的第一加密分支; 布置成生成所述标签的第二加密分支; 以及单个密钥调度单元，被配置为接收该密钥，以便基于该密钥生成至少一个子密钥，并将该至少一个子密钥提供给第一和第二加密分支。

2. 发明授权

US08233619B2 Implementation of AES encryption circuitry with CCM 有权
标题翻译：采用CCM实现AES加密电路
公开(公告)号：US08233619B2
公开(公告)日：2012-07-31
申请号：US11448425
申请日：2006-06-07
申请人： Guido Bertoni , Jefferson E. Owen
发明人： Guido Bertoni , Jefferson E. Owen
IPC分类号： H04K1/06
CPC分类号： H04L9/0631 , H04L9/0637 , H04L9/3242 , H04L2209/125 , H04L2209/24 , H04L2209/38 , H04L2209/80
摘要： Circuitry for encrypting at least a part of an input data flow and generating a tag based on the input data flow with the same ciphering algorithm and the same key, the algorithm including iterative computations by at least two operation units, the circuitry including a pipeline including an input selection unit arranged to receive first data values to generate encryption sequences with the ciphering algorithm, second data values to generate temporary tags with the ciphering algorithm and an output of the pipeline; a first stage arranged to receive an output of the input selection unit and including at least a first operation unit; and a second stage arranged to receive an output of the first stage, including at least a second operation unit and providing the output of the pipeline.
摘要翻译：电路，用于对输入数据流的至少一部分进行加密，并使用相同的加密算法和相同的密钥，基于输入数据流生成标签，所述算法包括由至少两个操作单元进行的迭代计算，所述电路包括流水线，输入选择单元，被配置为接收第一数据值以生成具有加密算法的加密序列，第二数据值以加密算法和流水线的输出生成临时标签; 第一级，被布置成接收输入选择单元的输出并且至少包括第一操作单元; 以及第二级，被布置成接收第一级的输出，包括至少第二操作单元并提供管道的输出。

3. 发明申请

US20070286416A1 Implementation of AES encryption circuitry with CCM 有权
标题翻译：采用CCM实现AES加密电路
公开(公告)号：US20070286416A1
公开(公告)日：2007-12-13
申请号：US11448425
申请日：2006-06-07
申请人： Guido Bertoni , Jefferson E. Owen
发明人： Guido Bertoni , Jefferson E. Owen
IPC分类号： H04K1/06
CPC分类号： H04L9/0631 , H04L9/0637 , H04L9/3242 , H04L2209/125 , H04L2209/24 , H04L2209/38 , H04L2209/80
摘要： Circuitry for encrypting at least a part of an input data flow and generating a tag based on the input data flow with the same ciphering algorithm and the same key, the algorithm including iterative computations by at least two operation units, the circuitry including a pipeline including an input selection unit arranged to receive first data values to generate encryption sequences with the ciphering algorithm, second data values to generate temporary tags with the ciphering algorithm and an output of the pipeline; a first stage arranged to receive an output of the input selection unit and including at least a first operation unit; and a second stage arranged to receive an output of the first stage, including at least a second operation unit and providing the output of the pipeline.
摘要翻译：电路，用于对输入数据流的至少一部分进行加密，并使用相同的加密算法和相同的密钥，基于输入数据流生成标签，所述算法包括由至少两个操作单元进行的迭代计算，所述电路包括流水线，输入选择单元，被配置为接收第一数据值以生成具有加密算法的加密序列，第二数据值以加密算法和流水线的输出生成临时标签; 第一级，被布置成接收输入选择单元的输出并且至少包括第一操作单元; 以及第二级，被布置成接收第一级的输出，包括至少第二操作单元并提供管道的输出。

4. 发明申请

US20070286415A1 AES encryption circuitry with CCM 有权
标题翻译：具有CCM的AES加密电路
公开(公告)号：US20070286415A1
公开(公告)日：2007-12-13
申请号：US11448424
申请日：2006-06-07
申请人： Guido Bertoni , Jefferson E. Owen
发明人： Guido Bertoni , Jefferson E. Owen
IPC分类号： H04K1/06
CPC分类号： H04L9/0631 , H04L9/0637 , H04L9/3242 , H04L2209/125 , H04L2209/24 , H04L2209/38 , H04L2209/80
摘要： Circuitry for encrypting at least a part of an input data flow and generating a tag based on the input data flow with the same ciphering algorithm and the same key including a first ciphering branch arranged to encrypt the at least part of the input data; a second ciphering branch arranged to generate the tag; and a single key schedule unit arranged to receive the key, to generate at least one sub-key based on the key and to provide the at least one sub-key to the first and second ciphering branches.
摘要翻译：电路，用于对输入数据流的至少一部分进行加密，并且以相同的加密算法和相同的密钥生成基于输入数据流的标签，该密钥包括布置成加密输入数据的至少部分的第一加密分支; 布置成生成所述标签的第二加密分支; 以及单个密钥调度单元，被配置为接收该密钥，以便基于该密钥生成至少一个子密钥，并将该至少一个子密钥提供给第一和第二加密分支。

5. 发明申请

US20120033806A1 METHOD OF ENCRYPTING A DATA STREAM 审中-公开
标题翻译：加密数据流的方法
公开(公告)号：US20120033806A1
公开(公告)日：2012-02-09
申请号：US13196568
申请日：2011-08-02
申请人： Guido Bertoni , Fabio Sozzani
发明人： Guido Bertoni , Fabio Sozzani
IPC分类号： H04L9/18
CPC分类号： H04L9/0662 , H04L2209/125
摘要： The disclosure relates to a method of encrypting or of decrypting a binary data stream by generating a binary encryption stream and combining by a reversible logic operation each bit of the binary data stream with a bit of the binary encryption stream, the generation of the binary encryption stream including generating an input block by applying a cryptographic function using a secret key to a data block, and generating the binary encryption stream from the input block by combining the bits of the input block with each other by logic operations in a manner so as to prevent the input block from being determined from the binary encryption stream.
摘要翻译：本公开涉及一种通过生成二进制加密流并通过可逆逻辑运算将二进制数据流的每一位与二进制加密流的位组合，二进制加密的生成来加密或解密二进制数据流的方法流，包括通过使用秘密密钥将加密功能应用于数据块来生成输入块，以及通过逻辑运算将输入块的比特相互组合来生成来自输入块的二进制加密流，以便防止从二进制加密流确定输入块。

6. 发明授权

US07206410B2 Circuit for the inner or scalar product computation in Galois fields 有权
标题翻译：伽罗瓦域内部或标量积计算电路
公开(公告)号：US07206410B2
公开(公告)日：2007-04-17
申请号：US09974176
申请日：2001-10-10
申请人： Guido Bertoni , Luca Breveglieri , Pasqualina Fragneto
发明人： Guido Bertoni , Luca Breveglieri , Pasqualina Fragneto
IPC分类号： G06F7/00
CPC分类号： G06F7/724
摘要： A circuit for computing the inner of scalar product of two vectors in a finite Galois field defined by a generator polynomial, wherein each vector includes at least two elements belonging to said finite field, comprises one or more look-up tables storing digital words indicative of said possible combinations and said possible reductions. The digital words in question are defined as a function of the second elements of said vectors and the generator polynomial of the field. The input register(s) and the look-up table(s) are configured to co-operate in a plurality of subsequent steps to generate at each step a partial product result identified by at least one of digital word addressed in a corresponding look-up table as a function of the digital signals stored in the input register(s). The circuit also includes an accumulator unit for adding up the partial results generated at each step to give a final product result deriving from accumulation of said partial results.
摘要翻译：一种用于计算由生成多项式定义的有限伽罗瓦域中的两个向量的标量积的内部的电路，其中每个向量包括属于所述有限域的至少两个元素，包括一个或多个查找表，其存储指示说可能的组合和所述可能的减少。所讨论的数字词被定义为所述向量的第二元素和场的生成多项式的函数。输入寄存器和查找表被配置为在多个后续步骤中协作以在每个步骤处生成由相应查找表中寻址的数字字中的至少一个标识的部分乘积结果，作为存储在输入寄存器中的数字信号的函数。该电路还包括用于将在每个步骤产生的部分结果相加以产生从所述部分结果的积累得到的最终产品结果的累加器单元。

7. 发明申请

US20060008084A1 Ciphering by blocks of the content of a memory external to a processor 有权
标题翻译：通过处理器外部存储器的内容的块进行加密
公开(公告)号：US20060008084A1
公开(公告)日：2006-01-12
申请号：US11175978
申请日：2005-07-06
申请人： Joan Daemen , Gilles Van Assche , Guido Bertoni
发明人： Joan Daemen , Gilles Van Assche , Guido Bertoni
IPC分类号： H04K1/00
CPC分类号： G06F21/85 , G06F12/1408 , G06F21/6209 , G06F2221/2107 , H04L9/0618 , H04L2209/12
摘要： A method and an element for ciphering with an integrated processor data to be stored in a memory, including applying to each data block to be ciphered a ciphering algorithm which is a function of at least one key specific to the integrated circuit, and before applying the ciphering algorithm thereto, combining the data block to be ciphered with the result of a function of the storage address of the ciphered block in the memory, and/or of combining the key with the result of a function of the storage address of the ciphered block in the memory and of a digital quantity different from the ciphering key.
摘要翻译：一种用于使用要存储在存储器中的集成处理器数据进行加密的方法和元件，包括应用到要加密的每个数据块，加密算法，其是集成电路特有的至少一个密钥的函数，并且在应用将加密的数据块与存储器中的加密块的存储地址的功能的结果组合，和/或将密钥与加密块的存储地址的功能的结果组合在存储器中和与加密密钥不同的数字量。

8. 再颁专利

USRE44594E1 Method and circuit for data encryption/decryption 有权
标题翻译：数据加密/解密的方法和电路
公开(公告)号：USRE44594E1
公开(公告)日：2013-11-12
申请号：US13456457
申请日：2012-05-29
申请人： Marco Macchetti , Stefano Marchesin , Umberto Bondi , Luca Breveglieri , Guido Bertoni , Pasqualina Fragneto
发明人： Marco Macchetti , Stefano Marchesin , Umberto Bondi , Luca Breveglieri , Guido Bertoni , Pasqualina Fragneto
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , H04L2209/12 , H04L2209/24
摘要： Data are converted between an unencrypted and an encrypted format according to the Rijndael algorithm, including a plurality of rounds. Each round is comprised of a fixed set of transformations applied to a two-dimensional array, designating states, of rows and columns of bit words. At least a part of the transformations are applied on a transposed version of the state, wherein rows and columns are transposed for the columns and rows, respectively.
摘要翻译：根据Rijndael算法，包括多个轮次，数据在未加密格式和加密格式之间进行转换。每一轮由应用于二维阵列的一组固定变换组成，指定位字的行和列的状态。至少一部分变换被应用在状态的转置版本上，其中行和列分别被转置用于列和行。

9. 发明授权

US08102997B2 Processor for executing an AES-type algorithm 有权
标题翻译：用于执行AES类型算法的处理器
公开(公告)号：US08102997B2
公开(公告)日：2012-01-24
申请号：US11547195
申请日：2004-03-29
申请人： Yannick Teglia , Fabrice Romain , Pierre-Yvan Liardet , Pasqualina Fragneto , Fabio Sozzani , Guido Bertoni
发明人： Yannick Teglia , Fabrice Romain , Pierre-Yvan Liardet , Pasqualina Fragneto , Fabio Sozzani , Guido Bertoni
IPC分类号： H04L9/28 , H04K1/00
CPC分类号： H04L9/0631 , H04L9/003 , H04L2209/046 , H04L2209/08 , H04L2209/122
摘要： A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register (102) containing an input data block column; an output register (111) containing an output data block column or an intermediate block column; a second input register (101) containing a key block column or the intermediate data blocks; a block substitution element (104) receiving the data one block at a time following the selection (103) thereof in the first register and providing, for each block, a column of blocks; an element (109) applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element (110) combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.
摘要翻译：一种用于执行Rijndeal算法的处理器，该Rijndeal算法将多个加密回合应用于数据块阵列，以便获得相同大小的阵列，每轮涉及密钥块阵列和数据块替换表，其中所述处理器包括：第一输入寄存器（102），其包含输入数据块列; 包含输出数据块列或中间块列的输出寄存器（111）; 包含密钥块列或中间数据块的第二输入寄存器（101）; 块替换元件（104）在第一寄存器中的选择（103）之后的时间接收数据一个块，并为每个块提供一列块; 向替代电路列块施加循环置换的元件（109）; 以及将置换电路列块与第二寄存器的内容组合的异或组合元件（110），所述组合的结果被加载到输出寄存器中。

10. 发明申请

US20070260664A1 Computation of a multiplication operation with an electronic circuit and method 有权
标题翻译：用电子电路和方法计算乘法运算
公开(公告)号：US20070260664A1
公开(公告)日：2007-11-08
申请号：US11786767
申请日：2007-04-11
申请人： Guido Bertoni , Pasqualina Fragneto , Andrew Marsh , Gerardo Pelosi , Moris Ravasio
发明人： Guido Bertoni , Pasqualina Fragneto , Andrew Marsh , Gerardo Pelosi , Moris Ravasio
IPC分类号： G06F7/38
CPC分类号： G06F7/728 , G06F7/722
摘要： A computing method and circuit for computing a modular operation with at least one operand having a binary representation. Iteratively for each bit of this operand, doubling the value of an intermediate result stored in a first memory element by shifting the bits of the intermediate result towards the most significant bit and, while the most significant bit of the intermediate result is one, updating this intermediate result by subtracting a modulus stored in a second memory element.
摘要翻译：一种用于利用具有二进制表示的至少一个操作数来计算模块化操作的计算方法和电路。迭代地对于该操作数的每个位，通过将中间结果的位移向最高有效位来将存储在第一存储元件中的中间结果的值加倍，并且当中间结果的最高有效位为1时，更新该值通过减去存储在第二存储元件中的模数的中间结果。

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