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1. 发明授权

US07831039B2 AES encryption circuitry with CCM 有权
标题翻译：具有CCM的AES加密电路
公开(公告)号：US07831039B2
公开(公告)日：2010-11-09
申请号：US11448424
申请日：2006-06-07
申请人： Guido Bertoni , Jefferson E. Owen
发明人： Guido Bertoni , Jefferson E. Owen
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28 , H04L9/32
CPC分类号： H04L9/0631 , H04L9/0637 , H04L9/3242 , H04L2209/125 , H04L2209/24 , H04L2209/38 , H04L2209/80
摘要： Circuitry for encrypting at least a part of an input data flow and generating a tag based on the input data flow with the same ciphering algorithm and the same key including a first ciphering branch arranged to encrypt the at least part of the input data; a second ciphering branch arranged to generate the tag; and a single key schedule unit arranged to receive the key, to generate at least one sub-key based on the key and to provide the at least one sub-key to the first and second ciphering branches.
摘要翻译：电路，用于对输入数据流的至少一部分进行加密，并且以相同的加密算法和相同的密钥生成基于输入数据流的标签，该密钥包括布置成加密输入数据的至少部分的第一加密分支; 布置成生成所述标签的第二加密分支; 以及单个密钥调度单元，被配置为接收该密钥，以便基于该密钥生成至少一个子密钥，并将该至少一个子密钥提供给第一和第二加密分支。

2. 发明授权

US08233619B2 Implementation of AES encryption circuitry with CCM 有权
标题翻译：采用CCM实现AES加密电路
公开(公告)号：US08233619B2
公开(公告)日：2012-07-31
申请号：US11448425
申请日：2006-06-07
申请人： Guido Bertoni , Jefferson E. Owen
发明人： Guido Bertoni , Jefferson E. Owen
IPC分类号： H04K1/06
CPC分类号： H04L9/0631 , H04L9/0637 , H04L9/3242 , H04L2209/125 , H04L2209/24 , H04L2209/38 , H04L2209/80
摘要： Circuitry for encrypting at least a part of an input data flow and generating a tag based on the input data flow with the same ciphering algorithm and the same key, the algorithm including iterative computations by at least two operation units, the circuitry including a pipeline including an input selection unit arranged to receive first data values to generate encryption sequences with the ciphering algorithm, second data values to generate temporary tags with the ciphering algorithm and an output of the pipeline; a first stage arranged to receive an output of the input selection unit and including at least a first operation unit; and a second stage arranged to receive an output of the first stage, including at least a second operation unit and providing the output of the pipeline.
摘要翻译：电路，用于对输入数据流的至少一部分进行加密，并使用相同的加密算法和相同的密钥，基于输入数据流生成标签，所述算法包括由至少两个操作单元进行的迭代计算，所述电路包括流水线，输入选择单元，被配置为接收第一数据值以生成具有加密算法的加密序列，第二数据值以加密算法和流水线的输出生成临时标签; 第一级，被布置成接收输入选择单元的输出并且至少包括第一操作单元; 以及第二级，被布置成接收第一级的输出，包括至少第二操作单元并提供管道的输出。

3. 发明申请

US20070286416A1 Implementation of AES encryption circuitry with CCM 有权
标题翻译：采用CCM实现AES加密电路
公开(公告)号：US20070286416A1
公开(公告)日：2007-12-13
申请号：US11448425
申请日：2006-06-07
申请人： Guido Bertoni , Jefferson E. Owen
发明人： Guido Bertoni , Jefferson E. Owen
IPC分类号： H04K1/06
CPC分类号： H04L9/0631 , H04L9/0637 , H04L9/3242 , H04L2209/125 , H04L2209/24 , H04L2209/38 , H04L2209/80
摘要： Circuitry for encrypting at least a part of an input data flow and generating a tag based on the input data flow with the same ciphering algorithm and the same key, the algorithm including iterative computations by at least two operation units, the circuitry including a pipeline including an input selection unit arranged to receive first data values to generate encryption sequences with the ciphering algorithm, second data values to generate temporary tags with the ciphering algorithm and an output of the pipeline; a first stage arranged to receive an output of the input selection unit and including at least a first operation unit; and a second stage arranged to receive an output of the first stage, including at least a second operation unit and providing the output of the pipeline.
摘要翻译：电路，用于对输入数据流的至少一部分进行加密，并使用相同的加密算法和相同的密钥，基于输入数据流生成标签，所述算法包括由至少两个操作单元进行的迭代计算，所述电路包括流水线，输入选择单元，被配置为接收第一数据值以生成具有加密算法的加密序列，第二数据值以加密算法和流水线的输出生成临时标签; 第一级，被布置成接收输入选择单元的输出并且至少包括第一操作单元; 以及第二级，被布置成接收第一级的输出，包括至少第二操作单元并提供管道的输出。

4. 发明申请

US20070286415A1 AES encryption circuitry with CCM 有权
标题翻译：具有CCM的AES加密电路
公开(公告)号：US20070286415A1
公开(公告)日：2007-12-13
申请号：US11448424
申请日：2006-06-07
申请人： Guido Bertoni , Jefferson E. Owen
发明人： Guido Bertoni , Jefferson E. Owen
IPC分类号： H04K1/06
CPC分类号： H04L9/0631 , H04L9/0637 , H04L9/3242 , H04L2209/125 , H04L2209/24 , H04L2209/38 , H04L2209/80
摘要： Circuitry for encrypting at least a part of an input data flow and generating a tag based on the input data flow with the same ciphering algorithm and the same key including a first ciphering branch arranged to encrypt the at least part of the input data; a second ciphering branch arranged to generate the tag; and a single key schedule unit arranged to receive the key, to generate at least one sub-key based on the key and to provide the at least one sub-key to the first and second ciphering branches.
摘要翻译：电路，用于对输入数据流的至少一部分进行加密，并且以相同的加密算法和相同的密钥生成基于输入数据流的标签，该密钥包括布置成加密输入数据的至少部分的第一加密分支; 布置成生成所述标签的第二加密分支; 以及单个密钥调度单元，被配置为接收该密钥，以便基于该密钥生成至少一个子密钥，并将该至少一个子密钥提供给第一和第二加密分支。

5. 发明授权

US6028612A Picture memory mapping to minimize memory bandwidth in compression and decompression of data sequences 失效
标题翻译：图像存储器映射以最小化数据序列的压缩和解压缩中的存储器带宽
公开(公告)号：US6028612A
公开(公告)日：2000-02-22
申请号：US972917
申请日：1997-11-18
申请人： Jeyendran Balakrishnan , Jefferson E. Owen
发明人： Jeyendran Balakrishnan , Jefferson E. Owen
IPC分类号： G06F12/04 , H04N5/907 , H04N7/26 , H04N7/50 , H04N9/804 , H04N9/808 , G06F12/06
CPC分类号： G06F12/0207 , H04N19/102 , H04N19/16 , H04N19/172 , H04N19/423 , H04N19/433 , H04N19/61
摘要： A method of a storing a picture in a memory such that bandwidth can be reduced when retrieving an array portion of the picture from the memory, and a memory architecture are disclosed. The memory is subdivided into a plurality of words for storing a picture having rows and columns. The picture is partitioned into two or more stripes each having a predetermined number of columns. The number of bytes in one row of one stripe is equal to the number of bytes in one word, for storing the data in one row of a stripe in one word. For the case of progressive video sequences or images the memory is organized in frame structure. For the case of interlaced video sequences or images, the memory is organized in field structure. For a frame picture to be stored in a frame organized memory or a field picture to be stored in a field organized memory, the data in the first row of one of the stripes is stored in a first word. The data in each subsequent row of the stripe is stored in a word having a word address adjacent and subsequent to the word storing the data of the directly preceding row. For a frame picture to be stored in a field organized memory, the odd rows are stored together according the above mapping scheme in a first memory buffer, and the even rows are stored together according to the above mapping scheme in a second memory buffer.
摘要翻译：一种将图像存储在存储器中的方法，使得可以在从存储器检索图像的阵列部分时减少带宽，并且公开了存储器架构。存储器被细分为用于存储具有行和列的图片的多个单词。图像被分割成两条或更多条，每条具有预定数量的列。一个条带的一行中的字节数等于一个字中的字节数，用于将数据存储在一行中的条带的一行中。对于逐行视频序列或图像的情况，存储器以帧结构组织。对于隔行视频序列或图像的情况，存储器以场结构组织。对于要存储在帧组织的存储器中的帧图像或要存储在场组织存储器中的场图像，其中一个条纹的第一行中的数据被存储在第一个字中。条带的每个后续行中的数据被存储在具有与存储前一行的数据的字相邻并在其之后的字地址的字中。对于要存储在场组织存储器中的帧画面，根据上述映射方案将奇数行存储在第一存储器缓冲器中，并且偶数行根据上述映射方案一起存储在第二存储器缓冲器中。

6. 发明授权

US5951690A Synchronizing an audio-visual stream synchronized to a clock with a video display that is synchronized to a different clock 失效
标题翻译：将与时钟同步的视听流同步到与不同时钟同步的视频显示
公开(公告)号：US5951690A
公开(公告)日：1999-09-14
申请号：US762608
申请日：1996-12-09
申请人： Yehuda Baron , Jefferson E. Owen , Darryn D. McDade
发明人： Yehuda Baron , Jefferson E. Owen , Darryn D. McDade
IPC分类号： G11B20/00 , G11B20/10 , G11B27/10 , G11B27/30 , H04N5/85 , H04N9/804 , H04N21/2368 , H04N21/434 , G06F1/12
CPC分类号： H04N9/8042 , G11B20/00007 , G11B20/10527 , G11B27/10 , G11B27/3027 , H04N21/4143 , H04N21/42646 , H04N21/4305 , H04N21/4307 , G11B2220/2562 , H04N5/85
摘要： A DVD player that integrates a DVD device into a personal computer is provided. As such, the personal computer is able to output audio-visual works from a DVD CD-ROM. When integrating a DVD device with a personal computer, various problems must be overcome. For example, in a personal computer, the video display is controlled by a graphics controller, and in order to render an audio-visual stream in a personal computer, the audio-visual stream and the graphics controller must be synchronized. The synchronization problem arises because the graphics controller only displays data at the beginning of 33.4 millisecond time intervals. Thus, although the audio portion may be played almost immediately, the video portion may have to wait for up to 33.4 milliseconds before being displayed. In this manner, the audio portion and the video portion become unsynchronized which means that the audio portion plays before the corresponding video portion is displayed. The DVD player solves this problem by synchronizing the start of the audio-visual stream with the graphics controller so that the time at which a video sequence is displayed coincides with one of the graphics controller's 33.4 millisecond time intervals.
摘要翻译：提供将DVD设备集成到个人计算机中的DVD播放器。因此，个人计算机能够从DVD CD-ROM输出视听作品。当将DVD设备与个人计算机集成时，必须克服各种问题。例如，在个人计算机中，视频显示由图形控制器控制，并且为了在个人计算机中呈现视听流，视听流和图形控制器必须同步。出现同步问题是因为图形控制器仅在33.4毫秒的时间间隔开始显示数据。因此，虽然可以立即播放音频部分，但是在显示之前视频部分可能必须等待多达33.4毫秒。以这种方式，音频部分和视频部分变得不同步，这意味着音频部分在相应的视频部分被显示之前播放。 DVD播放机通过将视听流的开始与图形控制器同步来解决这个问题，使得显示视频序列的时间与图形控制器的33.4毫秒时间间隔一致。

7. 发明授权

US5889515A Rendering an audio-visual stream synchronized by a software clock in a personal computer 失效
标题翻译：渲染由个人计算机中的软件时钟同步的视听流
公开(公告)号：US5889515A
公开(公告)日：1999-03-30
申请号：US762616
申请日：1996-12-09
申请人： Darryn D. McDade , Jefferson E. Owen
发明人： Darryn D. McDade , Jefferson E. Owen
IPC分类号： G06F1/12 , G06F1/08 , G06T1/00 , G11B20/00 , G11B27/10 , G11B27/30 , H04N5/04 , H04N5/765 , H04N5/92 , H04N7/26 , G06F17/00
CPC分类号： G11B20/00007 , G06F1/08 , G11B27/105 , G11B27/3027 , H04N5/765
摘要： A DVD CD-ROM player integrated with a personal computer is provided. When integrating a DVD CD-ROM with a personal computer, there are various problems that must be overcome. For example, the stream from the DVD CD-ROM utilizes a 27 MHz clock. However, a personal computer typically does not have a 27 MHz clock, but instead has a system clock, that runs at the frequency of the processor. Therefore, in order to play a DVD-based audio-visual work in a personal computer, a clock running at 27 MHz is needed. As such, a software clock running at 27 MHz is provided which facilitates the integration of a DVD CD-ROM into a personal computer. By using a software clock, synchronization of the audio-visual stream is facilitated and both cost and development time are reduced.
摘要翻译：提供与个人计算机集成的DVD CD-ROM播放器。当将DVD光盘与个人计算机集成时，存在必须克服的各种问题。例如，来自DVD CD-ROM的流使用27MHz时钟。然而，个人计算机通常不具有27MHz时钟，而是具有以处理器的频率运行的系统时钟。因此，为了在个人计算机中播放基于DVD的视听工作，需要以27MHz运行的时钟。因此，提供了以27MHz运行的软件时钟，其有助于将DVD CD-ROM集成到个人计算机中。通过使用软件时钟，便于视听流的同步，降低成本和开发时间。

8. 发明授权

US5305452A Bus controller with different microprocessor and bus clocks and emulation of different microprocessor command sequences 失效
标题翻译：总线控制器具有不同的微处理器和总线时钟，并仿真不同的微处理器命令序列
公开(公告)号：US5305452A
公开(公告)日：1994-04-19
申请号：US600297
申请日：1990-10-15
申请人： Rashid N. Khan , Robert W. Catlin , Jefferson E. Owen
发明人： Rashid N. Khan , Robert W. Catlin , Jefferson E. Owen
IPC分类号： G06F1/08 , G06F13/42 , G06F1/04
CPC分类号： G06F13/4217 , G06F1/08
摘要： The present invention provides a system whereby the microprocessor and the bus controller in a personal computer can be driven at different frequencies. Furthermore with the present invention the COMMAND DELAY and the WAIT STATE signals on the bus can be adjusted under program control.
摘要翻译：本发明提供了一种系统，其中可以以不同的频率驱动个人计算机中的微处理器和总线控制器。此外，通过本发明，总线上的COMMAND DELAY和等待状态信号可以在程序控制下进行调整。

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