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1. 发明授权

US10073625B2 Variable-RPM hard disk drive control 有权
公开(公告)号：US10073625B2
公开(公告)日：2018-09-11
申请号：US14989560
申请日：2016-01-06
申请人： HGST Netherlands B.V.
发明人： Cyril Guyot , Mohammed Ghiath Khatib , Adam C. Manzanares , Lluis Pamies-Juarez
IPC分类号： G06F1/32 , G06F3/06 , G11B19/26
CPC分类号： G06F3/0608 , G06F1/3203 , G06F3/0653 , G06F3/0689 , G06F11/00 , G11B19/2072 , G11B19/26 , G11B19/28
摘要： The present disclosure relates to a system and methods of controlling a system of storage devices. In particular, the present disclosure relates to methods of controlling peak power and energy consumption in storage systems due to storage devices while maintaining data availability. The system implements a method for maintaining data availability in a storage subsystem by determining a plurality of storage devices to include in a fixed set of storage devices based on a fault tolerance system. The storage devices included in the fixed set are prevented from transitioning between RPM spin modes. The method further involves controlling peak power and energy consumed by the storage subsystem which may include transitioning the storage devices not included in the fixed set from a high RPM operational mode to a low RPM operational mode to reduce peak power and energy consumption.

2. 发明申请

US20140101517A1 Encoding and Decoding Redundant Bits to Accommodate Memory Cells Having Stuck-At Faults 有权
标题翻译：冗余位的编码和解码以容纳存储单元卡住故障
公开(公告)号：US20140101517A1
公开(公告)日：2014-04-10
申请号：US13649108
申请日：2012-10-10
申请人： HGST NETHERLANDS B.V.
发明人： Robert Eugeniu Mateescu , Luiz Franca-Neto , Cyril Guyot , Hessam Mahdavifar , Zvonimir Bandic , Qingbo Wang
IPC分类号： G06F11/10
CPC分类号： G11C29/802 , G06F11/1048 , G11C29/52 , G11C2029/0411
摘要： A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults. The control circuit encodes the first set of redundant bits to generate a second set of redundant bits. The control circuit performs logic functions on the second set of redundant bits and the encoded data bits to generate a third set of redundant bits, such that redundant bits in the third set of redundant bits selected for storage in a second subset of the memory cells with second stuck-at faults have digital values of corresponding ones of the second stuck-at faults.
摘要翻译：数据存储系统具有包括存储器单元的存储器电路和接收提供用于存储在存储器单元中的数据位的控制电路。控制电路对数据位进行编码以产生第一组冗余位和编码数据位，使得被选择用于存储在具有第一个卡住故障的存储单元的第一子集中的编码数据位具有数字值第一个卡住的故障。控制电路对第一组冗余位进行编码以产生第二组冗余位。控制电路在第二组冗余位和编码数据位上执行逻辑功能以产生第三组冗余位，使得选择用于存储在存储器单元的第二子集中的第三组冗余位中的冗余位，第二个卡住的故障具有对应的第二个卡住故障的数字值。

3. 发明申请

US20140101516A1 Encoding and Decoding Data to Accommodate Memory Cells Having Stuck-At Faults 有权
标题翻译：编码和解码数据以容纳存储单元卡住故障
公开(公告)号：US20140101516A1
公开(公告)日：2014-04-10
申请号：US13649098
申请日：2012-10-10
申请人： HGST NETHERLANDS B.V.
发明人： Robert Eugeniu Mateescu , Luiz Franca-Neto , Cyril Guyot , Hessam Mahdavifar , Zvonimir Bandic , Qingbo Wang
IPC分类号： G06F11/10 , H03M13/15
CPC分类号： G06F11/1012 , G06F11/1008 , G06F11/108
摘要： A data storage system includes a memory circuit that has memory cells and a control circuit that is operable to receive data bits provided for storage in the memory cells. The control circuit is operable to receive a first matrix. Each row of the first matrix corresponds to a unique one of the data bits. The control circuit is operable to generate a second matrix having only the rows of the first matrix that correspond to the data bits provided for storage in a subset of the memory cells having stuck-at faults. The control circuit is operable to generate a third matrix having linearly independent columns of the second matrix. The control circuit is operable to encode the data bits to generate encoded data bits and redundant bits using the third matrix.
摘要翻译：数据存储系统包括具有存储器单元的存储器电路和可操作以接收提供用于存储在存储器单元中的数据位的控制电路。控制电路可操作以接收第一矩阵。第一矩阵的每行对应于唯一的一个数据位。控制电路可操作以产生仅具有第一矩阵的行的第二矩阵，该第一矩阵与提供用于存储在存在故障的存储器单元的子集中的数据位对应。控制电路可操作以产生具有第二矩阵的线性独立列的第三矩阵。控制电路可操作以对数据位进行编码，以使用第三矩阵生成编码数据位和冗余位。

4. 发明授权

US10078646B2 Hardware efficient fingerprinting 有权
公开(公告)号：US10078646B2
公开(公告)日：2018-09-18
申请号：US14835622
申请日：2015-08-25
申请人： HGST Netherlands B.V.
发明人： Zvonimir Bandic , Cyril Guyot , Dongyang Li , Ashwin Narasimha , Qingbo Wang , Ken Yang
IPC分类号： G06F17/30 , H03M7/30
CPC分类号： G06F16/215 , G06F16/2365 , H03M7/3091 , H03M7/3093 , H03M7/6029
摘要： An approach for fingerprinting large data objects at the wire speed has been disclosed. The techniques include Fresh/Shift pipelining, split Fresh, optimization, online channel sampling, and pipelined selection. The architecture can also be replicated to work in parallel for higher system throughput. Fingerprinting may provide an efficient mechanism for identifying duplication in a data stream, and deduplication based on the identified fingerprints may provide reduced storage costs, reduced network bandwidth consumption, reduced processing time and other benefits. In some embodiments, fingerprinting may be used to ensure or verify data integrity and may facilitate detection of corruption or tampering. An efficient manner of generating fingerprints (either via hardware, software, or a combination) may reduce a computation load and/or time required to generate fingerprints.

5. 发明申请

US20170192685A1 Variable-RPM Hard Disk Drive Control 审中-公开
公开(公告)号：US20170192685A1
公开(公告)日：2017-07-06
申请号：US14989560
申请日：2016-01-06
申请人： HGST Netherlands B.V.
发明人： Cyril Guyot , Mohammed Ghiath Khatib , Adam C. Manzanares , Lluis Pamies-Juarez
IPC分类号： G06F3/06 , G11B19/26
CPC分类号： G06F3/0608 , G06F1/3203 , G06F3/0653 , G06F3/0689 , G06F11/00 , G11B19/2072 , G11B19/26 , G11B19/28
摘要： The present disclosure relates to a system and methods of controlling a system of storage devices. In particular, the present disclosure relates to methods of controlling peak power and energy consumption in storage systems due to storage devices while maintaining data availability. The system implements a method for maintaining data availability in a storage subsystem by determining a plurality of storage devices to include in a fixed set of storage devices based on a fault tolerance system. The storage devices included in the fixed set are prevented from transitioning between RPM spin modes. The method further involves controlling peak power and energy consumed by the storage subsystem which may include transitioning the storage devices not included in the fixed set from a high RPM operational mode to a low RPM operational mode to reduce peak power and energy consumption.

6. 发明授权

US09471227B2 Implementing enhanced performance with read before write to phase change memory to avoid write cancellations 有权
标题翻译：在写入相变存储器之前，通过读取来实现增强的性能，以避免写入取消
公开(公告)号：US09471227B2
公开(公告)日：2016-10-18
申请号：US14332197
申请日：2014-07-15
申请人： HGST Netherlands B.V.
发明人： Cyril Guyot , Robert Eugeniu Mateescu , Dejan Vucinic
IPC分类号： G06F3/06 , G06F12/08 , G11C14/00 , G11C13/00
CPC分类号： G06F3/061 , G06F3/065 , G06F3/0677 , G06F12/0862 , G06F12/0893 , G06F2212/602 , G08B25/14 , G11C13/0002 , G11C13/0004 , G11C13/0069 , G11C14/009 , G11C2207/2236 , G11C2207/2245 , H04L12/2823 , H04L12/2825
摘要： A method, apparatus, and storage device are provided for implementing enhanced performance with read before write to phase-change-memory (PCM). Each write to PCM is preceded by a read to avoid write cancellations with urgent reads from nearby locations. For every write, a large block of data is read from PCM, such as an entire partition, prior to the write in PCM. The cache copy of the large block of data is kept in a controller for the duration of write. A read request from the pre-fetched region is provided from the cached copy thereby preventing read interrupt during write operation.
摘要翻译：提供了一种方法，装置和存储装置，用于在写入相变存储器（PCM）之前通过读取来实现增强的性能。每次写入PCM之前都要进行读取，以避免从附近位置紧急读取的写入取消。对于每次写入，在PCM写入之前，从PCM（例如整个分区）读取大量数据。在写入期间，大块数据的高速缓存副本保存在控制器中。从缓存的副本提供来自预取区域的读取请求，从而防止在写入操作期间的读取中断。

7. 发明授权

US09274884B2 Encoding and decoding data to accommodate memory cells having stuck-at faults 有权
标题翻译：编码和解码数据以适应存在故障的存储器单元
公开(公告)号：US09274884B2
公开(公告)日：2016-03-01
申请号：US13649098
申请日：2012-10-10
申请人： HGST Netherlands B.V.
发明人： Robert Eugeniu Mateescu , Luiz Franca-Neto , Cyril Guyot , Hessam Mahdavifar , Zvonimir Bandic , Qingbo Wang
IPC分类号： G06F11/00 , G06F11/10 , H03M13/00
CPC分类号： G06F11/1012 , G06F11/1008 , G06F11/108
摘要： A data storage system includes a memory circuit that has memory cells and a control circuit that is operable to receive data bits provided for storage in the memory cells. The control circuit is operable to receive a first matrix. Each row of the first matrix corresponds to a unique one of the data bits. The control circuit is operable to generate a second matrix having only the rows of the first matrix that correspond to the data bits provided for storage in a subset of the memory cells having stuck-at faults. The control circuit is operable to generate a third matrix having linearly independent columns of the second matrix. The control circuit is operable to encode the data bits to generate encoded data bits and redundant bits using the third matrix.
摘要翻译：数据存储系统包括具有存储器单元的存储器电路和可操作以接收提供用于存储在存储器单元中的数据位的控制电路。控制电路可操作以接收第一矩阵。第一矩阵的每行对应于唯一的一个数据位。控制电路可操作以产生仅具有第一矩阵的行的第二矩阵，该第二矩阵对应于提供用于存储在具有卡住故障的存储器单元的子集中的数据位。控制电路可操作以产生具有第二矩阵的线性独立列的第三矩阵。控制电路可操作以对数据位进行编码，以使用第三矩阵生成编码数据位和冗余位。

8. 发明申请

US20150154120A1 ACOUSTICALLY SECURE PHASE CHANGE MEMORY DEVICES 有权
标题翻译：安全的相位改变存储设备
公开(公告)号：US20150154120A1
公开(公告)日：2015-06-04
申请号：US14096921
申请日：2013-12-04
申请人： HGST Netherlands B.V.
发明人： Cyril Guyot , Dejan Vucinic , Luiz Franca-Neto
IPC分类号： G06F12/14 , G11C13/00
CPC分类号： G06F12/1408 , G06F12/0238 , G06F2212/1052 , G11C13/0004 , G11C13/0059 , G11C13/0069 , G11C13/0097
摘要： Systems, methods, and firmware for operating data storage devices and storage processors are provided herein. In one example, a data storage device is provided. The data storage device includes phase change media on which to write data, and a processing system configured to identify a write process to at least obfuscate an acoustic signature associated with writing the data on the phase change media and write the data to the phase change media in accordance with the write process.
摘要翻译：本文提供了用于操作数据存储设备和存储处理器的系统，方法和固件。在一个示例中，提供了数据存储设备。数据存储装置包括用于写入数据的相变介质，以及处理系统，其被配置为识别写入处理，以至少模糊与相变媒体上的数据写入相关联的声学签名，并将该数据写入相变媒体按照写入过程。

9. 发明申请

US20140164821A1 Techniques For Encoding and Decoding Using a Combinatorial Number System 有权
标题翻译：使用组合数字系统进行编码和解码的技术
公开(公告)号：US20140164821A1
公开(公告)日：2014-06-12
申请号：US13712929
申请日：2012-12-12
申请人： HGST NETHERLANDS B.V.
发明人： Cyril Guyot , Luiz Franca-Neto , Robert Eugeniu Mateescu , Hessam Mahdavifar , Zvonimir Bandic , Qingbo Wang
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/1012 , H03M13/13
摘要： A data storage system includes a memory circuit having memory cells and a control circuit. The control circuit is operable to receive data bits provided for storage in the memory cells. A subset of the memory cells have predetermined stuck-at faults. The control circuit is operable to compute a binomial coefficient for each of the predetermined stuck-at faults based on a bit position of a corresponding one of the predetermined stuck-at faults within the memory cells. The control circuit is operable to add together the binomial coefficients to generate an encoded number using a combinatorial number system. The control circuit is operable to generate a first set of redundant bits that indicate the encoded number. The first set of redundant bits are used to decode bits read from the memory cells to regenerate the data bits.
摘要翻译：数据存储系统包括具有存储单元和控制电路的存储器电路。控制电路可操作以接收提供用于存储在存储器单元中的数据位。存储器单元的子集具有预定的卡住故障。控制电路可操作以基于存储器单元内的预定卡入故障中对应的一个的位位置来计算每个预定卡入故障的二项式系数。控制电路可操作以将二进制系数相加在一起，以使用组合数系统来生成编码数。控制电路可操作以产生指示编码数的第一组冗余位。第一组冗余位用于解码从存储器单元读取的位以再生数据位。

10. 发明申请

US20130124942A1 Techniques For Storing Data in Stuck and Unstable Memory Cells 有权
标题翻译：将数据存储在不稳定的存储单元中的技术
公开(公告)号：US20130124942A1
公开(公告)日：2013-05-16
申请号：US13649007
申请日：2012-10-10
申请人： HGST NETHERLANDS B.V.
发明人： Luiz Franca-Neto , Robert Eugeniu Mateescu , Cyril Guyot
IPC分类号： G06F11/10 , H03M13/13
CPC分类号： G06F11/1008
摘要： A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault value to the stuck-at fault value. The control circuit is operable to generate encoded data bits by inverting each of the data bits having a different value than the stuck-at fault value of the corresponding one of the memory cells and by maintaining a digital value of each of the data bits having the stuck-at fault value of the corresponding one of the memory cells. The control circuit is operable to prevent any of the data bits from being stored in the memory cells determined to have unstable values. The control circuit is operable to generate redundant bits that indicate at least one operation to perform on the encoded data bits to regenerate the data bits.
摘要翻译：数据存储系统包括存储器电路和控制电路。控制电路可操作以接收提供用于存储在存储器电路的存储单元中的数据位。控制电路可操作以将存储在具有卡住故障值的存储单元中的相应一个存储单元中的每个数据位与卡入故障值进行比较。控制电路可操作以通过将具有与相应的一个存储器单元的卡入故障值不同的值的每个数据位反相并通过保持每个数据位的数字值具有卡住相应的一个存储单元的故障值。控制电路可操作以防止任何数据位被存储在被确定为具有不稳定值的存储器单元中。控制电路可操作以产生指示对编码数据位执行的至少一个操作以再生数据位的冗余位。

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