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1. 发明授权

US12028094B2 Application programming interface for fine grained low latency decompression within processor core 有权
公开(公告)号：US12028094B2
公开(公告)日：2024-07-02
申请号：US17133622
申请日：2020-12-23
申请人： Intel Corporation
发明人： Jayesh Gaur , Adarsh Chauhan , Vinodh Gopal , Vedvyas Shanbhogue , Sreenivas Subramoney , Wajdi Feghali
IPC分类号： H03M7/00 , G06F9/38 , G06F9/54 , H03M7/30
CPC分类号： H03M7/6029 , G06F9/3877 , G06F9/541
摘要： Methods and apparatus relating to an Application Programming Interface (API) for fine grained low latency decompression within a processor core are described. In an embodiment, a decompression Application Programming Interface (API) receives an input handle to a data object. The data object includes compressed data and metadata. Decompression Engine (DE) circuitry decompresses the compressed data to generate uncompressed data. The DE circuitry decompress the compressed data in response to invocation of a decompression instruction by the decompression API. The metadata comprises a first operand to indicate a location of the compressed data, a second operand to indicate a size of the compressed data, a third operand to indicate a location to which decompressed data by the DE circuitry is to be stored, and a fourth operand to indicate a size of the decompressed data. Other embodiments are also disclosed and claimed.

2. 发明公开

US20240143410A1 TECHNOLOGIES FOR DIVIDING WORK ACROSS ACCELERATOR DEVICES 审中-公开
公开(公告)号：US20240143410A1
公开(公告)日：2024-05-02
申请号：US18405679
申请日：2024-01-05
申请人： Intel Corporation
发明人： Susanne M. Balle , Francesc Guim Bernat , Slawomir Putyrski , Joe Grecco , Henry Mitchel , Evan Custodio , Rahul Khanna , Sujoy Sen
IPC分类号： G06F9/50 , G06F3/06 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/38 , G06F9/4401 , G06F9/455 , G06F9/48 , G06F9/54 , G06F11/07 , G06F11/30 , G06F11/34 , G06F12/02 , G06F12/06 , G06F13/16 , G06F16/174 , G06F21/57 , G06F21/62 , G06F21/73 , G06F21/76 , G06T1/20 , G06T1/60 , G06T9/00 , H01R13/453 , H01R13/631 , H03K19/173 , H03M7/30 , H03M7/40 , H03M7/42 , H04L9/08 , H04L12/28 , H04L12/46 , H04L41/044 , H04L41/0816 , H04L41/0853 , H04L41/12 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L49/104 , H04L61/5007 , H04L67/10 , H04L67/1014 , H04L67/63 , H04L67/75 , H05K7/14
CPC分类号： G06F9/505 , G06F3/0604 , G06F3/0608 , G06F3/0611 , G06F3/0613 , G06F3/0617 , G06F3/0641 , G06F3/0647 , G06F3/065 , G06F3/0653 , G06F3/067 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/3851 , G06F9/3891 , G06F9/4401 , G06F9/45533 , G06F9/4843 , G06F9/4881 , G06F9/5005 , G06F9/5038 , G06F9/5044 , G06F9/5083 , G06F9/544 , G06F11/0709 , G06F11/0751 , G06F11/079 , G06F11/3006 , G06F11/3034 , G06F11/3055 , G06F11/3079 , G06F11/3409 , G06F12/0284 , G06F12/0692 , G06F13/1652 , G06F16/1744 , G06F21/57 , G06F21/6218 , G06F21/73 , G06F21/76 , G06T1/20 , G06T1/60 , G06T9/005 , H01R13/453 , H01R13/4536 , H01R13/4538 , H01R13/631 , H03K19/1731 , H03M7/3084 , H03M7/40 , H03M7/42 , H03M7/60 , H03M7/6011 , H03M7/6017 , H03M7/6029 , H04L9/0822 , H04L12/2881 , H04L12/4633 , H04L41/044 , H04L41/0816 , H04L41/0853 , H04L41/12 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L49/104 , H04L61/5007 , H04L67/10 , H04L67/1014 , H04L67/63 , H04L67/75 , H05K7/1452 , H05K7/1487 , H05K7/1491 , H04L47/78
摘要： Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.

3. 发明授权

US11687264B2 Technologies for accelerator interface 有权
公开(公告)号：US11687264B2
公开(公告)日：2023-06-27
申请号：US15721053
申请日：2017-09-29
申请人： Intel Corporation
发明人： Chih-Jen Chang , Brad Burres , Jose Niell , Dan Biederman , Robert Cone , Pat Wang , Kenneth Keels , Patrick Fleming
IPC分类号： H04L67/63 , G06F3/06 , G06F16/174 , G06F21/57 , G06F21/73 , G06F8/65 , H04L41/0816 , H04L41/0853 , H04L41/12 , H04L67/10 , G06F11/30 , G06F9/50 , H01R13/453 , G06F9/48 , G06F9/455 , H05K7/14 , H04L61/5007 , H04L67/75 , H03M7/30 , H03M7/40 , H04L43/08 , H04L47/20 , H04L47/2441 , G06F11/07 , G06F11/34 , G06F7/06 , G06T9/00 , H03M7/42 , H04L12/28 , H04L12/46 , G06F13/16 , G06F21/62 , G06F21/76 , H03K19/173 , H04L9/08 , H04L41/044 , H04L49/104 , H04L43/04 , H04L43/06 , H04L43/0894 , G06F9/38 , G06F12/02 , G06F12/06 , G06T1/20 , G06T1/60 , G06F9/54 , H04L67/1014 , G06F8/656 , G06F8/658 , G06F8/654 , G06F9/4401 , H01R13/631 , H04L47/78 , G06F16/28 , H04Q11/00 , G06F11/14 , H04L41/046 , H04L41/0896 , H04L41/142 , H04L9/40 , G06F15/80
CPC分类号： G06F3/0641 , G06F3/0604 , G06F3/065 , G06F3/067 , G06F3/0608 , G06F3/0611 , G06F3/0613 , G06F3/0617 , G06F3/0647 , G06F3/0653 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/3851 , G06F9/3891 , G06F9/4401 , G06F9/45533 , G06F9/4843 , G06F9/4881 , G06F9/5005 , G06F9/505 , G06F9/5038 , G06F9/5044 , G06F9/5083 , G06F9/544 , G06F11/0709 , G06F11/079 , G06F11/0751 , G06F11/3006 , G06F11/3034 , G06F11/3055 , G06F11/3079 , G06F11/3409 , G06F12/0284 , G06F12/0692 , G06F13/1652 , G06F16/1744 , G06F21/57 , G06F21/6218 , G06F21/73 , G06F21/76 , G06T1/20 , G06T1/60 , G06T9/005 , H01R13/453 , H01R13/4536 , H01R13/4538 , H01R13/631 , H03K19/1731 , H03M7/3084 , H03M7/40 , H03M7/42 , H03M7/60 , H03M7/6011 , H03M7/6017 , H03M7/6029 , H04L9/0822 , H04L12/2881 , H04L12/4633 , H04L41/044 , H04L41/0816 , H04L41/0853 , H04L41/12 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L49/104 , H04L61/5007 , H04L67/10 , H04L67/1014 , H04L67/63 , H04L67/75 , H05K7/1452 , H05K7/1487 , H05K7/1491 , G06F11/1453 , G06F12/023 , G06F15/80 , G06F16/285 , G06F2212/401 , G06F2212/402 , G06F2221/2107 , H04L41/046 , H04L41/0896 , H04L41/142 , H04L47/78 , H04L63/1425 , H04Q11/0005 , H05K7/1447 , H05K7/1492
摘要： Technologies for an accelerator interface over Ethernet are disclosed. In the illustrative embodiment, a network interface controller of a compute device may receive a data packet. If the network interface controller determines that the data packet should be pre-processed (e.g., decrypted) with a remote accelerator device, the network interface controller may encapsulate the data packet in an encapsulating network packet and send the encapsulating network packet to a remote accelerator device on a remote compute device. The remote accelerator device may pre-process the data packet (e.g., decrypt the data packet) and send it back to the network interface controller. The network interface controller may then send the pre-processed packet to a processor of the compute device.

4. 发明申请

US20180152200A1 TECHNOLOGIES FOR DETERMINISTIC CONSTANT-TIME DATA COMPRESSION 审中-公开
公开(公告)号：US20180152200A1
公开(公告)日：2018-05-31
申请号：US15720920
申请日：2017-09-29
申请人： Intel Corporation
发明人： James D. Guilford , Vinodh Gopal , Daniel F. Cutter
IPC分类号： H03M7/30 , G06F7/06 , H03M7/42 , G06T9/00
CPC分类号： G06F3/0641 , G06F3/0604 , G06F3/0608 , G06F3/0611 , G06F3/0613 , G06F3/0617 , G06F3/0647 , G06F3/065 , G06F3/0653 , G06F3/067 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/3851 , G06F9/3891 , G06F9/4401 , G06F9/4881 , G06F9/5038 , G06F9/505 , G06F9/544 , G06F11/0709 , G06F11/0751 , G06F11/079 , G06F11/1453 , G06F11/3006 , G06F11/3034 , G06F11/3055 , G06F11/3409 , G06F12/023 , G06F12/0284 , G06F12/0692 , G06F13/1652 , G06F15/80 , G06F17/30153 , G06F21/57 , G06F21/6218 , G06F21/73 , G06F21/76 , G06F2212/401 , G06F2212/402 , G06F2221/2107 , G06T1/20 , G06T1/60 , G06T9/005 , H01R13/4538 , H01R13/631 , H03K19/1731 , H03M7/3084 , H03M7/40 , H03M7/42 , H03M7/60 , H03M7/6011 , H03M7/6017 , H03M7/6029 , H04L9/0822 , H04L12/2881 , H04L12/4633 , H04L41/044 , H04L41/046 , H04L41/0816 , H04L41/0853 , H04L41/0896 , H04L41/12 , H04L41/142 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L49/104 , H04L61/2007 , H04L63/1425 , H04L67/10 , H04L67/1014 , H04L67/327 , H04L67/36 , H05K7/1452 , H05K7/1487
摘要： A compute device to generate deterministic compressed streams receives a current string to be matched to one or more prior instances of the current string, the current string being located within an input buffer and the one or more prior instances located within a history buffer. The compute device identifies a limited subset of index memory designated for storing pointers to the prior instances, identifying a reserved slop region in the index memory, and compares the current string to a prior instance, locating the at least one prior instance using at least one pointer to the at least one prior instance. The at least one pointer is stored within the limited subset of the index memory, and the compute device also prohibits use of any pointers stored in the reserved slop region of the index memory. Other embodiments are described and claimed.

5. 发明申请

US20180150372A1 TECHNOLOGIES FOR PROVIDING MANIFEST-BASED ASSET REPRESENTATION 审中-公开
公开(公告)号：US20180150372A1
公开(公告)日：2018-05-31
申请号：US15826051
申请日：2017-11-29
申请人： Intel Corporation
发明人： Murugasamy K. Nachimuthu , Mohan J. Kumar , Alberto J. Munoz
IPC分类号： G06F11/30 , G06F3/06
CPC分类号： G06F3/0641 , G06F3/0604 , G06F3/0608 , G06F3/0611 , G06F3/0613 , G06F3/0617 , G06F3/0647 , G06F3/065 , G06F3/0653 , G06F3/067 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/3851 , G06F9/3891 , G06F9/4401 , G06F9/4881 , G06F9/5038 , G06F9/505 , G06F9/544 , G06F11/0709 , G06F11/0751 , G06F11/079 , G06F11/1453 , G06F11/3006 , G06F11/3034 , G06F11/3055 , G06F11/3409 , G06F12/023 , G06F12/0284 , G06F12/0692 , G06F13/1652 , G06F15/80 , G06F16/1744 , G06F21/57 , G06F21/6218 , G06F21/73 , G06F21/76 , G06F2212/401 , G06F2212/402 , G06F2221/2107 , G06T1/20 , G06T1/60 , G06T9/005 , H01R13/4538 , H01R13/631 , H03K19/1731 , H03M7/3084 , H03M7/40 , H03M7/42 , H03M7/60 , H03M7/6011 , H03M7/6017 , H03M7/6029 , H04L9/0822 , H04L12/2881 , H04L12/4633 , H04L41/044 , H04L41/046 , H04L41/0816 , H04L41/0853 , H04L41/0896 , H04L41/12 , H04L41/142 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L47/78 , H04L49/104 , H04L61/2007 , H04L63/1425 , H04L67/10 , H04L67/1014 , H04L67/327 , H04L67/36 , H05K7/1452 , H05K7/1487
摘要： Technologies for generating manifest data for a sled include a sled to generate manifest data indicative of one or more characteristics of the sled (e.g., hardware resources, firmware resources, a configuration of the sled, or a health of sled components). The sled is also to associate an identifier with the manifest data. The identifier uniquely identifies the sled from other sleds. Additionally, the sled is to send the manifest data and the associated identifier to a server. The sled may also detect a change in the hardware resources, firmware resources, the configuration, or component health of the sled. The sled may also generate an update of the manifest data based on the detected change, where the update specifies the detected change in the hardware resources, firmware resources, the configuration, or component health of the sled. The sled may also send the update of the manifest data to the server.

6. 发明授权

US09532044B2 Arithmetic decoding device, image decoding apparatus and arithmetic decoding method 有权
标题翻译：算术解码装置，图像解码装置和算术解码方法
公开(公告)号：US09532044B2
公开(公告)日：2016-12-27
申请号：US14225207
申请日：2014-03-25
申请人： PANASONIC CORPORATION
发明人： Yuya Shigenobu
IPC分类号： H04N19/13 , H03M7/40 , H04N19/91 , H04N19/436 , H03M7/30 , H04N19/61
CPC分类号： H04N19/13 , H03M7/4018 , H03M7/6029 , H04N19/436 , H04N19/61 , H04N19/91
摘要： An arithmetic decoding device includes a calculating unit that calculates candidates for split information using probability information, the split information indicating a boundary between a first value range and a second value range in range information, the probability information indicating whether a next item of binary data takes the first or second value, and the range information indicating a possible range of positional information obtained from a stream; a selecting unit that selects the split information corresponding to the range information from among the candidates; and a generating unit that generates the binary data according to which range of the range information divided at the split information includes the positional information and generates a next piece of the range information and a next piece of the positional information using the generated binary data. A process of the calculating unit and that of the generating unit are pipelined.
摘要翻译：一种算术解码装置，包括使用概率信息计算分割信息的候选的计算单元，表示范围信息中的第一值范围和第二值范围之间的边界的分割信息，所述概率信息表示下一个二进制数据项是否需要第一或第二值，以及指示从流获得的位置信息的可能范围的范围信息; 选择单元，从所述候选中选择与所述范围信息对应的分割信息; 以及生成单元，根据分割信息划分的范围信息的范围，生成二进制数据，并且使用生成的二进制数据生成下一个范围信息和下一个位置信息。计算单元和生成单元的处理被流水线化。

7. 发明申请

US20160224595A1 Hardware Efficient Fingerprinting 审中-公开
标题翻译：硬件高效指纹
公开(公告)号：US20160224595A1
公开(公告)日：2016-08-04
申请号：US14835622
申请日：2015-08-25
申请人： HGST Netherlands B.V.
发明人： Zvonimir Bandic , Cyril Guyot , Dongyang Li , Ashwin Narasimha , Qingbo Wang , Ken Yang
IPC分类号： G06F17/30
CPC分类号： G06F17/30303 , G06F17/30371 , H03M7/3091 , H03M7/3093 , H03M7/6029
摘要： An approach for fingerprinting large data objects at the wire speed has been disclosed. The techniques include Fresh/Shift pipelining, split Fresh, optimization, online channel sampling, and pipelined selection. The architecture can also be replicated to work in parallel for higher system throughput. Fingerprinting may provide an efficient mechanism for identifying duplication in a data stream, and deduplication based on the identified fingerprints may provide reduced storage costs, reduced network bandwidth consumption, reduced processing time and other benefits. In some embodiments, fingerprinting may be used to ensure or verify data integrity and may facilitate detection of corruption or tampering. An efficient manner of generating fingerprints (either via hardware, software, or a combination) may reduce a computation load and/or time required to generate fingerprints.
摘要翻译：已经公开了一种以线速指纹大数据对象的方法。这些技术包括Fresh / Shift流水线，分离新鲜，优化，在线通道采样和流水线选择。还可以将架构复制到并行工作以实现更高的系统吞吐量。指纹可以提供用于识别数据流中的重复的有效机制，并且基于所识别的指纹的重复数据消除可以提供降低的存储成本，减少的网络带宽消耗，减少的处理时间和其他益处。在一些实施例中，可以使用指纹来确保或验证数据完整性，并且可以便于检测到损坏或篡改。生成指纹（通过硬件，软件或组合）的有效方式可以减少生成指纹所需的计算负荷和/或时间。

8. 发明授权

US09124295B2 System and method for data compression and transmission 有权
标题翻译：用于数据压缩和传输的系统和方法
公开(公告)号：US09124295B2
公开(公告)日：2015-09-01
申请号：US14080248
申请日：2013-11-14
申请人： Nicolas Thomas Mathieu Dupont
发明人： Nicolas Thomas Mathieu Dupont
IPC分类号： H03M7/00 , H03M7/30 , H03M7/42
CPC分类号： H03M7/6029 , H03M7/30 , H03M7/42
摘要： A system, method, and apparatus for compressing binary code comprising at least a processor, memory, storage, and an encoding device or decoding device or both. The methods include comparing a given binary code string having a certain size to be compressed or decompressed with a table comprising all possible combinations of zeroes and ones for any binary data of size x. The given binary code string and all possible combinations are partitioned in packets of size y and each packet assigned a value. A second value representing an assembly of all the values into a second value is performed. The assembly may be performed n times to obtain an nth value. The second or nth value is transmitted or received or both by the encoding and decoding devices, respectively, in place of the given binary code. Table comparison may be performed using pattern recognition.
摘要翻译：一种用于压缩二进制码的系统，方法和装置，包括至少包括处理器，存储器，存储器，编码设备或解码设备或两者。所述方法包括将具有一定大小的给定二进制代码串与包括大小为x的任何二进制数据的零和一的所有可能组合的表进行压缩或解压缩。给定的二进制代码串和所有可能的组合在大小为y的数据包中进行分区，每个数据包都分配一个值。表示将所有值的组合表示为第二值的第二值。该组件可以执行n次以获得第n个值。第二或第n值分别由编码和解码装置发送或接收，或代替给定的二进制码。可以使用模式识别执行表比较。

9. 发明授权

US08847798B2 Systems and methods for data compression and parallel, pipelined decompression 有权
标题翻译：用于数据压缩和并行，流水线解压缩的系统和方法
公开(公告)号：US08847798B2
公开(公告)日：2014-09-30
申请号：US13717188
申请日：2012-12-17
申请人： Maxeler Technologies Ltd.
发明人： Oliver Pell , Stephen Girdlestone , Henning Meyer
IPC分类号： H03M7/30 , H03M5/14
CPC分类号： H03M5/145 , H03M7/30 , H03M7/46 , H03M7/6023 , H03M7/6029
摘要： A method of data compression includes obtaining a data set comprising a sequence of data blocks comprising a predetermined number of data items, partitioning said data set into one or more groups each comprising a predetermined number of data blocks, and performing data compression on one or more groups of data blocks. Data compression is performed by associating a control data item with each of said blocks, generating a control vector comprising the control data items assigned to each of said blocks within a group, removing data blocks comprising entirely data items having said specified value, compressing data blocks comprising at least one data item having a value different from said specified value using a fixed-rate compression scheme, providing a compressed data stream comprising said compressed data blocks, and providing an associated control vector stream to enable control of said compressed data stream.
摘要翻译：一种数据压缩方法包括获得包括包括预定数量的数据项的数据块序列的数据集，将所述数据集划分为一个或多个组，每个组包括预定数量的数据块，并且对一个或多个数据进行数据压缩数据块组。通过将控制数据项与每个所述块相关联来执行数据压缩，产生包括分配给组内的每个所述块的控制数据项的控制向量，去除包含完全具有所述指定值的数据项的数据块，压缩数据块包括使用固定速率压缩方案具有不同于所述指定值的值的至少一个数据项，提供包括所述压缩数据块的压缩数据流，以及提供关联的控制向量流以使得能够控制所述压缩数据流。

10. 发明授权

US08106799B1 Data compression and decompression using parallel processing 有权
标题翻译：使用并行处理的数据压缩和解压缩
公开(公告)号：US08106799B1
公开(公告)日：2012-01-31
申请号：US12728726
申请日：2010-03-22
申请人： Xueshi Yang , Gregory Burd
发明人： Xueshi Yang , Gregory Burd
IPC分类号： H03M7/00
CPC分类号： H03M7/3086 , H03M7/6023 , H03M7/6029
摘要： The present disclosure includes apparatus, systems and techniques relating to pipelined processing. In some implementations, a method performed by a data processing device includes storing data in a memory module. The method includes processing the stored data in accordance with a compression algorithm to produce processed data. Processing the stored data includes pipelined processing of a defined number of symbols of the stored data in parallel, and discarding results of the pipelined processing that are rendered invalid by other results of the pipelined processing. Additionally, the method includes outputting the processed data.
摘要翻译：本公开包括与流水线处理相关的装置，系统和技术。在一些实现中，由数据处理设备执行的方法包括将数据存储在存储器模块中。该方法包括根据压缩算法对所存储的数据进行处理以产生处理后的数据。处理存储的数据包括并行地存储的数据的定义数量的符号的流水线处理，以及通过流水线处理的其他结果废弃被流水线处理的结果无效的结果。另外，该方法包括输出处理的数据。

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