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1. 发明申请

US20100164568A1 LOW POWER VARIABLE DELAY CIRCUIT 有权
标题翻译：低功耗可变延迟电路
公开(公告)号：US20100164568A1
公开(公告)日：2010-07-01
申请号：US12636901
申请日：2009-12-14
申请人： Hae-Rang CHOI , Yong-Ju KIM , Sung-Woo HAN , Hee-Woong SONG , Ic-Su OH , Hyung-Soo KIM , Tae-Jin HWANG , Ji-Wang LEE , Jae-Min JANG , Chang-Kun PARK
发明人： Hae-Rang CHOI , Yong-Ju KIM , Sung-Woo HAN , Hee-Woong SONG , Ic-Su OH , Hyung-Soo KIM , Tae-Jin HWANG , Ji-Wang LEE , Jae-Min JANG , Chang-Kun PARK
IPC分类号： H03L7/00
CPC分类号： G11C19/28
摘要： A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.
摘要翻译：可变延迟电路至少包括固定延迟单元，第一选择单元和可变延迟单元。固定延迟单元接收表示第一延迟的输入信号和第一延迟选择信号，并且输出基本上延迟了第一延迟的输入信号的第一延迟信号。第一选择单元接收输入信号，第一延迟信号和第二延迟选择信号，并且基于第二延迟选择信号将输入信号或第一延迟信号输出到可变延迟单元。可变延迟单元还接收表示第三延迟的第三延迟选择信号，并且输出基本上延迟了第三延迟的选择单元的输出信号的输出信号。第一个延迟是M个延迟单位的0或X倍。第三延迟是从0到N个延迟单元中选择的延迟。

2. 发明申请

US20090147883A1 DATA TRANSMITTER 失效
标题翻译：数据传输器
公开(公告)号：US20090147883A1
公开(公告)日：2009-06-11
申请号：US12164948
申请日：2008-06-30
申请人： Hae-Rang CHOI , Kun-Woo Park , Yong-Ju Kim , Hee-Wong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee
发明人： Hae-Rang CHOI , Kun-Woo Park , Yong-Ju Kim , Hee-Wong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee
IPC分类号： H04L27/04
CPC分类号： G11C7/1051 , G11C7/1057 , H04L25/4902 , H04L25/4917
摘要： Data transmitter includes a first and second output nodes terminated to a first level, a controller configured to generate an off signal that is activated by logically combining first and second data during a low-power mode, a first driver configured to drive the first or second output node to a second level in response to the first data and a second driver configured to drive the first or second output node to the second level with a driving force different from that of the first driver in response to the second data, the second driver being turned off when the off signal is activated.
摘要翻译：数据发射机包括终止于第一电平的第一和第二输出节点，被配置为产生通过在低功率模式期间逻辑地组合第一和第二数据而被激活的关闭信号的控制器，配置成驱动第一或第二电平的第一驱动器输出节点响应于第一数据到第二级，第二驱动器被配置为响应于第二数据以与第一驱动器不同的驱动力将第一或第二输出节点驱动到第二级，第二驱动器当关闭信号被激活时被关闭。

3. 发明申请

US20120194239A1 DELAY LOCKED LOOP 有权
标题翻译：延迟锁定环
公开(公告)号：US20120194239A1
公开(公告)日：2012-08-02
申请号：US13111568
申请日：2011-05-19
申请人： Jae-Min JANG , Yong-Ju KIM , Hae-Rang CHOI
发明人： Jae-Min JANG , Yong-Ju KIM , Hae-Rang CHOI
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , G11C7/222 , H03L7/0814 , H03L7/0816
摘要： A DLL circuit includes a common delay line configured to generate a delay locked clock by selectively delaying a source clock by one or more unit delays in response to a first delay control code or a second delay control code, a clock cycle detector configured to compare a phase of the source clock with a phase of the delay locked clock in a cycle detection mode and generate the first delay control code corresponding to a delay amount of a cycle of the source clock based on a result of comparing the phases of the source and delay locked clocks, a feedback delay configured to delay the delay locked clock and output a feedback clock, and a delay amount controller configured to compare the phase of the source clock with a phase of the feedback clock in a delay locking mode and change the second delay control code based on a result of comparing the source and feedback clocks.
摘要翻译： DLL电路包括公共延迟线，其配置为通过响应于第一延迟控制代码或第二延迟控制代码选择性地将源时钟延迟一个或多个单位延迟来产生延迟锁定时钟，时钟周期检测器被配置为源时钟的相位以延迟锁定时钟的相位处于周期检测模式，并且基于比较源极和延迟的相位的结果生成与源时钟的周期的延迟量相对应的第一延迟控制代码锁定时钟，被配置为延迟延迟锁定时钟并输出反馈时钟的反馈延迟，以及延迟量控制器，被配置为将延迟锁定模式中的源时钟的相位与反馈时钟的相位进行比较，并且改变第二延迟基于比较源和反馈时钟的结果的控制代码。

4. 发明申请

US20110267117A1 DATA INPUT/OUTPUT APPARATUS AND METHOD FOR SEMICONDUCTOR SYSTEM 有权
标题翻译：数据输入/输出设备和半导体系统的方法
公开(公告)号：US20110267117A1
公开(公告)日：2011-11-03
申请号：US12832312
申请日：2010-07-08
申请人： Hae-Rang CHOI , Yong-Ju Kim , Jae-Min Jang
发明人： Hae-Rang CHOI , Yong-Ju Kim , Jae-Min Jang
IPC分类号： H03L7/06 , H03L7/00
CPC分类号： H03L7/00
摘要： A semiconductor memory device includes: a strobe signal reception unit configured to receive a strobe signal and generate a tracking clock signal; a clock reception unit configured to receive a clock signal and generate an internal clock signal; a plurality of data reception units configured to receive parallel data in accordance with the internal clock signal and generate internal data; and a phase control unit configured to control the phase of the internal clock signal to track the tracking clock signal and to compensate for a variation in the phase of the internal clock signal while the data is received.
摘要翻译：半导体存储器件包括：选通信号接收单元，被配置为接收选通信号并产生跟踪时钟信号; 时钟接收单元，被配置为接收时钟信号并产生内部时钟信号; 多个数据接收单元，被配置为根据内部时钟信号接收并行数据并产生内部数据; 以及相位控制单元，被配置为控制内部时钟信号的相位以跟踪跟踪时钟信号，并且在接收数据时补偿内部时钟信号的相位的变化。

5. 发明申请

US20110309867A1 PHASE LOCKED LOOP 有权
标题翻译：相位锁定环
公开(公告)号：US20110309867A1
公开(公告)日：2011-12-22
申请号：US12916901
申请日：2010-11-01
申请人： Hae-Rang CHOI , Yong-Ju Kim , Jae-Min Jang
发明人： Hae-Rang CHOI , Yong-Ju Kim , Jae-Min Jang
IPC分类号： H03L7/08
CPC分类号： H03L7/14 , H03L7/113
摘要： A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal.
摘要翻译：锁相环包括相位检测器，被配置为将输入时钟的相位与反馈时钟的相位进行比较以产生相位比较结果，初始频率值提供器被配置为检测输入时钟的频率并提供频率检测结果，配置为基于相位比较结果和频率检测结果产生频率控制信号的控制器，以及响应于频率控制信号产生输出时钟的振荡器。

6. 发明申请

US20090257537A1 DATA RECOVERY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS THAT MINIMIZES JITTER DURING DATA TRANSMISSION 审中-公开
标题翻译：在数据传输期间最小化抖动的半导体存储器的数据恢复电路
公开(公告)号：US20090257537A1
公开(公告)日：2009-10-15
申请号：US12344736
申请日：2008-12-29
申请人： Yong-Ju KIM , Hae-Rang CHOI , Oh-Kyong KWON , Jun-Yong SONG , Min-Seok SHIN
发明人： Yong-Ju KIM , Hae-Rang CHOI , Oh-Kyong KWON , Jun-Yong SONG , Min-Seok SHIN
IPC分类号： H04L7/00
CPC分类号： H04L7/0338 , G11C7/1012 , G11C7/1051 , G11C7/1066 , G11C7/222 , H03K5/135
摘要： A data recovery circuit that minimizes jitter during data transmission is presented. The data recovery circuit includes a data dividing unit, a data sampling unit, a data selecting unit, and a data recovery unit. The data dividing unit is for dividing external data to generate multiple-division data. The data sampling unit is for sampling the multiple-division data at a first time and a second time to generate sampling data. The data selecting unit is for selecting one of the data sampled at the first time or the second time from the sampling data in accordance to whether the sampling data is transited to output the selected one as selection data. The data recovery unit is for recovering the selection data to internal data in the same logic level as the logic level of the external data.
摘要翻译：呈现数据传输中抖动最小化的数据恢复电路。数据恢复电路包括数据分割单元，数据采样单元，数据选择单元和数据恢复单元。数据分割单元用于分割外部数据以产生多分割数据。数据采样单元用于在第一时间和第二时间对多分割数据进行采样以产生采样数据。数据选择单元用于根据抽样数据是否被转换以输出所选择的数据作为选择数据，用于从采样数据中选择在第一时间或第二时间采样的数据中的一个。数据恢复单元用于将选择数据恢复到与外部数据的逻辑电平相同的逻辑电平的内部数据。

7. 发明申请

US20130033294A1 COUNTING CIRCUIT OF SEMICONDUCTOR DEVICE AND DUTY CORRECTION CIRCUIT OF SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：使用其的半导体器件的半导体器件的计数电路和占空比校正电路
公开(公告)号：US20130033294A1
公开(公告)日：2013-02-07
申请号：US13366425
申请日：2012-02-06
申请人： Hae-Rang CHOI , Yong-Ju Kim
发明人： Hae-Rang CHOI , Yong-Ju Kim
IPC分类号： H03K3/017 , H03K23/00
CPC分类号： H03K5/1565 , H03K21/38
摘要： A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.
摘要翻译：半导体器件的计数电路包括多个计数单元，其被配置为分别响应于多个计数时钟对计数代码的各个位进行计数，并且响应于计数控制信号而在计数方向上进行控制; 时钟切换控制单元，被配置为响应于时钟控制信号来控制在多个计数时钟之间切换的计数时钟的数量; 以及计数操作控制单元，被配置为比较目标代码的值和计数代码的值，并且根据比较结果确定计数控制信号的值。

8. 发明申请

US20120112824A1 FILTER CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME 有权
标题翻译：滤波电路和集成电路，包括它们
公开(公告)号：US20120112824A1
公开(公告)日：2012-05-10
申请号：US12981161
申请日：2010-12-29
申请人： Hae-Rang CHOI , Young-Ju Kim
发明人： Hae-Rang CHOI , Young-Ju Kim
IPC分类号： H03K5/00
CPC分类号： G11C19/287 , H03H17/026 , H03H17/0283
摘要： A filter circuit includes a plurality of shifting units configured to each store an initial value, receive at least one input signal, and shift the stored value to a next shifting unit in sequence from among the shifting units in response to at least one input signal, and an initial value setting unit configured to set the initial stored values of the shifting units to different sets of initial stored values in response to different filter setting signals, respectively, wherein the different filter setting signals represent respectively different criteria for filtering the at least one input signal, wherein the initially stored values have a first logic value or a second logic value, wherein the filter circuit is configured to activate an output signal when the first logic value is shifted to a selected shifting unit among the plurality of shifting units.
摘要翻译：滤波器电路包括多个移位单元，每个移位单元被配置为每个存储初始值，接收至少一个输入信号，并且响应于至少一个输入信号，从移位单元中顺序地将存储的值移位到下一个移位单元，以及初始值设定单元，被配置为分别响应于不同的滤波器设置信号将移位单元的初始存储值设置为不同的初始存储值集合，其中不同的滤波器设置信号分别表示用于过滤至少一个输入信号，其中所述初始存储的值具有第一逻辑值或第二逻辑值，其中所述滤波器电路被配置为当所述多个移位单元中的所述第一逻辑值移位到所选择的移位单元时激活输出信号。

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