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1. 发明申请

US20100164568A1 LOW POWER VARIABLE DELAY CIRCUIT 有权
标题翻译：低功耗可变延迟电路
公开(公告)号：US20100164568A1
公开(公告)日：2010-07-01
申请号：US12636901
申请日：2009-12-14
申请人： Hae-Rang CHOI , Yong-Ju KIM , Sung-Woo HAN , Hee-Woong SONG , Ic-Su OH , Hyung-Soo KIM , Tae-Jin HWANG , Ji-Wang LEE , Jae-Min JANG , Chang-Kun PARK
发明人： Hae-Rang CHOI , Yong-Ju KIM , Sung-Woo HAN , Hee-Woong SONG , Ic-Su OH , Hyung-Soo KIM , Tae-Jin HWANG , Ji-Wang LEE , Jae-Min JANG , Chang-Kun PARK
IPC分类号： H03L7/00
CPC分类号： G11C19/28
摘要： A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.
摘要翻译：可变延迟电路至少包括固定延迟单元，第一选择单元和可变延迟单元。固定延迟单元接收表示第一延迟的输入信号和第一延迟选择信号，并且输出基本上延迟了第一延迟的输入信号的第一延迟信号。第一选择单元接收输入信号，第一延迟信号和第二延迟选择信号，并且基于第二延迟选择信号将输入信号或第一延迟信号输出到可变延迟单元。可变延迟单元还接收表示第三延迟的第三延迟选择信号，并且输出基本上延迟了第三延迟的选择单元的输出信号的输出信号。第一个延迟是M个延迟单位的0或X倍。第三延迟是从0到N个延迟单元中选择的延迟。

2. 发明申请

US20110001533A1 SAMPLING CIRCUIT 有权
标题翻译：采样电路
公开(公告)号：US20110001533A1
公开(公告)日：2011-01-06
申请号：US12630021
申请日：2009-12-03
申请人： Ji-Wang LEE , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang LEE , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03K3/00 , G06F7/42 , G06G7/12
CPC分类号： H03K3/356139 , G06F5/06 , H03K3/0375
摘要： A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.
摘要翻译：一种用于半导体器件的采样电路，包括：第一采样单元，被配置为与参考时钟信号同步地采样数据信号并输出第一输出信号;第二采样单元，被配置为与延迟数据信号同步采样参考时钟信号并输出第二输出信号，以及输出单元，被配置为组合第一和第二输出信号并输出采样数据信号。

3. 发明申请

US20110156772A1 INTERFACE APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND INTERFACING METHOD THEREOF 有权
标题翻译：用于半导体集成电路的接口装置及其接口方法
公开(公告)号：US20110156772A1
公开(公告)日：2011-06-30
申请号：US12650122
申请日：2009-12-30
申请人： Ji-Wang LEE , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Wang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang LEE , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Wang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03L7/06
CPC分类号： H03K19/0175 , H03K5/1565
摘要： An interface apparatus for a semiconductor integrated circuit and an interfacing method thereof controls the VOX of differential signals to a target level in response to the differential signals being outputted by an output block. The interface apparatus for a semiconductor integrated circuit includes an output block configured to output differential signals output by an internal circuit a detector configured to detect a timing error of the differential signals; and a controller configured to control a timing of the differential signals output by the internal circuit according to a detection result of the detector.
摘要翻译：半导体集成电路的接口装置及其接口方法响应于由输出块输出的差分信号，将差分信号的VOX控制到目标电平。用于半导体集成电路的接口装置包括：输出块，被配置为输出由内部电路输出的差分信号;检测器，被配置为检测差分信号的定时误差; 以及控制器，被配置为根据检测器的检测结果来控制由内部电路输出的差分信号的定时。

4. 发明申请

US20090273995A1 APPARATUS FOR REMOVING CROSSTALK IN SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：用于在半导体存储器件中移除晶体管的装置
公开(公告)号：US20090273995A1
公开(公告)日：2009-11-05
申请号：US12347518
申请日：2008-12-31
申请人： Ji-Wang LEE , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi
发明人： Ji-Wang LEE , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/02 , G11C5/063 , G11C7/1078 , G11C7/1084
摘要： An apparatus for removing crosstalk in a semiconductor memory device includes pads for receiving externally provided signals, transmission lines for delivering the signals received by each of the pads to corresponding elements in the apparatus, and capacitors, coupled between adjacent ones of the lines, for adjusting the transmission delay of the signals depending on a signal transmission mode between the adjacent lines.
摘要翻译：一种用于去除半导体存储器件中的串扰的装置包括用于接收外部提供的信号的焊盘，用于将由每个焊盘接收的信号传递到设备中的相应元件的传输线以及耦合在相邻线之间的电容器，以便调整信号的传输延迟取决于相邻线路之间的信号传输模式。

5. 发明申请

US20150294705A1 ELECTRONIC DEVICE 有权
标题翻译：电子设备
公开(公告)号：US20150294705A1
公开(公告)日：2015-10-15
申请号：US14563690
申请日：2014-12-08
申请人： Ji-Wang LEE , Dong-Keun KIM , Masahiro TAKAHASHI , Tsuneo INABA
发明人： Ji-Wang LEE , Dong-Keun KIM , Masahiro TAKAHASHI , Tsuneo INABA
IPC分类号： G11C11/16 , G11C13/00
CPC分类号： G11C11/1673 , G11C11/15 , G11C11/16 , G11C11/1659 , G11C11/5607 , G11C11/5657 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C16/28 , G11C2013/0054 , G11C2213/79
摘要： A semiconductor memory unit includes first to Nth variable resistance elements each having different resistance values according to values stored therein, wherein N is a natural number equal to or greater than 2; a reference resistance element having a first reference resistance value; and first to Nth comparison units which correspond to the first to Nth variable resistance elements, respectively, and each of which determines whether a resistance value of the corresponding variable resistance element is greater or less than a second reference resistance value, wherein the first to Nth comparison units are commonly coupled to the reference resistance element.
摘要翻译：半导体存储单元包括根据存储在其中的值具有不同电阻值的第一至第N可变电阻元件，其中N是等于或大于2的自然数; 具有第一参考电阻值的参考电阻元件; 以及分别对应于第一至第N可变电阻元件的第一至第N比较单元，并且每个比较单元确定相应的可变电阻元件的电阻值是否大于或小于第二参考电阻值，其中第一至第N 比较单元通常耦合到参考电阻元件。

6. 发明申请

US20120140870A1 INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME 失效
标题翻译：集成电路及其驱动方法
公开(公告)号：US20120140870A1
公开(公告)日：2012-06-07
申请号：US12980643
申请日：2010-12-29
申请人： Ji-Wang LEE , Shin-Deok KANG
发明人： Ji-Wang LEE , Shin-Deok KANG
IPC分类号： H03K23/00
CPC分类号： G06F1/10 , H03K21/406 , H03K23/425
摘要： An integrated circuit includes a counter configured to perform a counting operation and output a count code value. The integrated circuit further includes an operation controller, a digital circuit and an alignment unit. The operation controller receives the count code value and generates a first control signal and a second control signal. The first control signal is generated, when the count code value is equal to a first value, which is counted by the counter prior to a target count value. The second control signal is generated, when the count code value is equal to the target count value. A digital circuit performs a first operation based on the first control signal, and output a digital signal. An alignment unit aligns the digital signal, and outputs the aligned digital signal as a final digital signal in response to the second control signal.
摘要翻译：集成电路包括配置为执行计数操作并输出计数代码值的计数器。集成电路还包括操作控制器，数字电路和对准单元。操作控制器接收计数代码值并产生第一控制信号和第二控制信号。当计数码值等于由计数器在目标计数值之前计数的第一值时，产生第一控制信号。当计数码值等于目标计数值时，产生第二控制信号。数字电路基于第一控制信号执行第一操作，并输出数字信号。对准单元对准数字信号，并响应于第二控制信号而输出对准的数字信号作为最终的数字信号。

7. 发明申请

US20130113515A1 IMPEDANCE CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
标题翻译：阻抗控制电路和包括其的半导体器件
公开(公告)号：US20130113515A1
公开(公告)日：2013-05-09
申请号：US13446527
申请日：2012-04-13
申请人： Ji-Wang LEE
发明人： Ji-Wang LEE
IPC分类号： H03K19/003
CPC分类号： H03K19/018571 , H03K19/0005 , H03K19/018585
摘要： An impedance control circuit includes a first impedance unit configured to terminate an impedance node using an impedance value that is determined by an impedance control code, a second impedance unit configured to terminate the impedance node using an impedance value that is determined by an impedance control voltage, a comparison circuit configured to compare a voltage level of the impedance node and a voltage level of a reference voltage, generate an up/down signal indicating whether the voltage at the impedance node is greater than the reference voltage, and generate the impedance control voltage that has a voltage level corresponding to a difference between the voltage at the impedance node and the reference voltage, and a counter unit configured to increase or decrease a value of the impedance control code in response to the up/down signal.
摘要翻译：阻抗控制电路包括：第一阻抗单元，被配置为使用由阻抗控制代码确定的阻抗值来终止阻抗节点;第二阻抗单元，被配置为使用由阻抗控制电压确定的阻抗值来终止阻抗节点比较电路，被配置为比较阻抗节点的电压电平和参考电压的电压电平，生成表示阻抗节点处的电压是否大于参考电压的上/下信号，并产生阻抗控制电压其具有对应于阻抗节点处的电压与参考电压之间的差的电压电平，以及配置为响应于上/下信号增加或减少阻抗控制代码的值的计数器单元。

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