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1. 发明授权

US08471625B1 Beta enhanced voltage reference circuit 有权
标题翻译： β增强型电压基准电路
公开(公告)号：US08471625B1
公开(公告)日：2013-06-25
申请号：US13047313
申请日：2011-03-14
申请人： Hao Zhou , Bingkun Yao , Tao Shui , Yonghua Song
发明人： Hao Zhou , Bingkun Yao , Tao Shui , Yonghua Song
IPC分类号： G05F3/16 , H02M3/145
CPC分类号： G05F3/30
摘要： A beta enhancement circuit includes a current source connected in series with a transistor between two voltage supply lines. In an embodiment, the voltage supply lines are configured for connection to a power source and ground potential. A resistor device is connected between a control terminal of the transistor device and one of voltage supply lines. A value for the resistor device is selected based on one or more process dependent parameters of the transistor.
摘要翻译： β增强电路包括与两个电压线之间的晶体管串联连接的电流源。在一个实施例中，电压供应线被配置为连接到电源和地电位。电阻器件连接在晶体管器件的控制端子和电源线之一之间。基于晶体管的一个或多个处理相关参数来选择电阻器件的值。

2. 发明授权

US07990225B1 Low-jitter phase-locked loop 有权
标题翻译：低抖动锁相环
公开(公告)号：US07990225B1
公开(公告)日：2011-08-02
申请号：US12498989
申请日：2009-07-07
申请人： Jianmin Guo , Yihui Li , Hong Xue , Yonghua Song , Tao Shui , Hao Zhou
发明人： Jianmin Guo , Yihui Li , Hong Xue , Yonghua Song , Tao Shui , Hao Zhou
IPC分类号： H03L7/085
CPC分类号： H03L7/099 , H03L7/093 , H03L2207/06
摘要： A phase-locked loop (PLL) with a decreased frequency tuning gain KVCO and a loop filter using capacitor multiplication technique to get high chip area efficiency. To get decreased frequency tuning gain, KVCO, a voltage to current converter in a voltage-controlled oscillator (VCO) in the PLL may comprise a first voltage to current converter and a second voltage to current converter. The trans-conductance of the first voltage to current converter is 1/β of that of the second voltage to current converter, wherein β>1. The first voltage to current converter is controlled by an output voltage of a loop filter in the PLL, and the second voltage to current converter is controlled by a relative DC voltage, which may be the junction node between R1 and C1 in a loop filer of the PLL. Capacitor multiplication technique may use an auxiliary charge pump to charge or discharge the junction node between R1 and C1 inversely to the main charge pump. When the charge or discharge current unit of the auxiliary charge pump is α times of the main charge pump, the capacitance of C1 may be reduced to just (1−α) times of what it needed in a conventional loop stability compensation method, wherein α
摘要翻译：具有降低的频率调谐增益KVCO的锁相环（PLL）和使用电容器乘法技术的环路滤波器以获得高芯片面积效率。为了降低频率调谐增益，PLL中的压控振荡器（VCO）中的电压 - 电流转换器KVCO可以包括第一电压 - 电流转换器和第二电压 - 电流转换器。第一个电压到电流转换器的反向电导为1 / 的第二电压到电流转换器，其中＆amp; 1。第一个电压到电流转换器由PLL中的环路滤波器的输出电压控制，第二个电压到电流转换器由一个相对直流电压控制，相对直流电压可以是一个环路滤波器中的R1和C1之间的结点 PLL。电容倍增技术可以使用辅助电荷泵来将R1和C1之间的连接节点与主电荷泵反向充电或放电。当辅助电荷泵的充电或放电电流单元是主电荷泵的α倍时，C1的电容可以降低到常规环路稳定性补偿方法中所需要的（1-α）倍，其中α <1。

3. 发明授权

US08451160B1 Low power high speed pipeline ADC 有权
标题翻译：低功耗高速流水线ADC
公开(公告)号：US08451160B1
公开(公告)日：2013-05-28
申请号：US13109320
申请日：2011-05-17
申请人： Hao Zhou , Yonghua Song , Tao Shui , Jie Jiang , Song Chen
发明人： Hao Zhou , Yonghua Song , Tao Shui , Jie Jiang , Song Chen
IPC分类号： H03M1/38
CPC分类号： H03M1/002 , H03M1/1215 , H03M1/124 , H03M1/167
摘要： In accordance with the teachings described herein, systems and methods are provided for a time-interleaved pipeline analog to digital converter. An example pipeline analog to digital converter may include passive sampling circuits and a multiplying digital to analog converter circuit. A first passive sampling circuit includes an input terminal coupled to an analog input signal, and outputs a first sample voltage that is responsive to the analog input signal. A second passive sampling circuit includes an input terminal coupled to the analog input signal, and outputs a second sample voltage that is responsive to the analog input signal. The first and second passive sampling circuits are clocked such that the first sample voltage and the second sample voltage are time-interleaved. A multiplying analog to digital converter (MDAC) circuit receives the time-interleaved first and second sample voltages from the first and second passive sampling circuits and processes the time-interleaved first and second sample voltages to generate a residue output voltage.
摘要翻译：根据本文描述的教导，为时间交错流水线模数转换器提供了系统和方法。示例性管线模数转换器可以包括无源采样电路和乘法数模转换器电路。第一无源采样电路包括耦合到模拟输入信号的输入端，并且输出响应于模拟输入信号的第一采样电压。第二无源采样电路包括耦合到模拟输入信号的输入端，并且输出响应于模拟输入信号的第二采样电压。第一和第二无源采样电路被计时，使得第一采样电压和第二采样电压是时间交织的。乘法模数转换器（MDAC）电路接收来自第一和第二无源采样电路的时间交错的第一和第二采样电压，并处理时间交错的第一和第二采样电压以产生残余输出电压。

4. 发明授权

US09190859B1 Voltage reference buffer using voltage battery level shifter 有权
标题翻译：电压参考缓冲器使用电压电池电平转换器
公开(公告)号：US09190859B1
公开(公告)日：2015-11-17
申请号：US13115813
申请日：2011-05-25
申请人： Hao Zhou , Yonghua Song , Tao Shui , Jie Jiang
发明人： Hao Zhou , Yonghua Song , Tao Shui , Jie Jiang
IPC分类号： H02J7/00
CPC分类号： H03K17/161 , H02J7/0054 , H03K17/063 , H03K2217/0081
摘要： In one embodiment, an apparatus includes a first supply voltage and a second supply voltage. Level shifter circuitry is configured as a first voltage battery to shift a first voltage and a second voltage battery to shift a second voltage. A first circuit receives the shifted first voltage and sets a third voltage, and receives the shifted second voltage and sets a fourth voltage. The shifted first voltage is greater than the first supply voltage and the shifted second voltage level is less than the second supply voltage. A second circuit sets a fifth voltage and a sixth voltage. The fifth voltage follows the third voltage and the sixth voltage following the fourth voltage.
摘要翻译：在一个实施例中，装置包括第一电源电压和第二电源电压。电平移位器电路被配置为第一电压电池以移动第一电压和第二电压电池以移位第二电压。第一电路接收移位的第一电压并设置第三电压，并接收移位的第二电压并设置第四电压。移位的第一电压大于第一电源电压，并且移位的第二电压电平小于第二电源电压。第二电路设置第五电压和第六电压。第五电压跟随第四电压的第三电压和第六电压。

5. 发明授权

US08354887B1 Charge compensation for operational transconductance amplifier based circuits 有权
标题翻译：基于运算跨导放大器的电路的充电补偿
公开(公告)号：US08354887B1
公开(公告)日：2013-01-15
申请号：US13109315
申请日：2011-05-17
申请人： Hao Zhou , Yonghua Song , Jie Jiang , Tao Shui
发明人： Hao Zhou , Yonghua Song , Jie Jiang , Tao Shui
IPC分类号： H03F1/14
CPC分类号： H03F3/45188 , H03F3/45695 , H03F3/70 , H03F2200/456 , H03F2203/45318 , H03F2203/45332 , H03F2203/45354 , H03F2203/45356
摘要： In accordance with the teachings described herein, systems and methods are provided for charge compensation. A system may include an operational transconductance amplifier including an input terminal and an output terminal, a transistor network, and a capacitive circuit. The transistor network may be coupled in a feedback loop between the input terminal and the output terminal. The capacitive circuit may be configured to compensate a charge built on a parasitic capacitance of the transistor network during operation.
摘要翻译：根据本文所述的教导，提供了用于电荷补偿的系统和方法。系统可以包括一个包括输入端和输出端，晶体管网络和电容电路的运算跨导放大器。晶体管网络可以在输入端子和输出端子之间的反馈回路中耦合。电容电路可以被配置为补偿在操作期间内置于晶体管网络的寄生电容上的电荷。

6. 发明授权

US09184839B1 Method and apparatus for compensating impairments in radio frequency circuitry of a wireless device 有权
标题翻译：用于补偿无线设备的射频电路中的损伤的方法和装置
公开(公告)号：US09184839B1
公开(公告)日：2015-11-10
申请号：US13566157
申请日：2012-08-03
申请人： Songping Wu , Daxiao Yu , Yonghua Song
发明人： Songping Wu , Daxiao Yu , Yonghua Song
IPC分类号： H04B10/2507 , H04B17/20
CPC分类号： H04B17/17
摘要： The present disclosure describes techniques for identity-based RF circuitry compensation. In some aspects data from a wireless device is received via radio frequency circuitry, the data including an identifier that uniquely identifies the wireless device. Impairments of the radio frequency circuitry are estimated based on the received data and then the estimated impairments are associated with the identifier of the wireless device. In response to subsequently receiving data that includes the identifier, the radio frequency circuitry is compensated using the estimated impairments.
摘要翻译：本公开描述了用于基于身份的RF电路补偿的技术。在一些方面，来自无线设备的数据经由射频电路接收，该数据包括唯一地标识无线设备的标识符。基于接收到的数据来估计射频电路的损害，然后估计的损伤与无线设备的标识符相关联。响应于随后接收包括标识符的数据，使用估计的损伤来补偿射频电路。

7. 发明授权

US07664204B1 Adaptive timing using clock recovery 有权
标题翻译：使用时钟恢复的自适应时序
公开(公告)号：US07664204B1
公开(公告)日：2010-02-16
申请号：US11078717
申请日：2005-03-10
申请人： Hui Wang , Yonghua Song
发明人： Hui Wang , Yonghua Song
IPC分类号： H04L27/00 , H03D3/24
CPC分类号： H04L27/0014 , H04L2027/0036 , H04L2027/0053 , H04L2027/0065 , H04L2027/0067 , H04L2027/0091
摘要： Circuits and methods are provided for adjusting a frequency of a local clock signal in approximating a frequency of a host clock signal. A phase locked loop generates a local clock signal having a first phase and a first frequency. An offset adjustment circuit receives timing information relating the local clock signal to an incoming data signal and calculates a phase offset and a frequency offset indicative of adjustments to be made to the local clock signal. A first phase interpolator generates a receive clock signal from the local clock signal, the receive clock signal having a second phase and a second frequency responsive to the phase and frequency offsets. A second phase interpolator generates a transmit clock signal from the local clock signal having a third frequency responsive to the frequency offset.
摘要翻译：提供电路和方法，用于在近似主机时钟信号的频率时调整本地时钟信号的频率。锁相环产生具有第一相位和第一频率的本地时钟信号。偏移调整电路接收与输入数据信号相关的本地时钟信号的定时信息，并计算出相应的偏移和指示对本地时钟信号进行调整的频率偏移。第一相位内插器从本地时钟信号产生接收时钟信号，接收时钟信号具有响应于相位和频率偏移的第二相位和第二频率。第二相位插值器响应于频率偏移从具有第三频率的本地时钟信号产生发送时钟信号。

8. 发明授权

US07528657B1 Baseband filter start-up circuit 有权
标题翻译：基带滤波器启动电路
公开(公告)号：US07528657B1
公开(公告)日：2009-05-05
申请号：US11699890
申请日：2007-01-30
申请人： Donghong Cui , Yonghua Song
发明人： Donghong Cui , Yonghua Song
IPC分类号： H03F3/45
CPC分类号： H03F3/45094 , H03F1/34 , H03F3/45475 , H03F3/72 , H03F2203/45521
摘要： An electrical circuit comprises a plurality of amplifiers. Each of the plurality of amplifiers comprises an input circuit in communication with an input of the amplifier and a start-up circuit in communication with the input circuit. The start-up circuit is configured to generate a start-up signal to enable subsequent operation of the amplifier. An output circuit communicates with an output of the amplifier and with the input circuit and the start-up circuit. Respective inputs of a first and a second amplifier of the plurality of amplifiers are in communication with outputs of a third amplifier of the plurality of amplifiers. Outputs of the second amplifier are in communication with inputs of the third amplifier.
摘要翻译：电路包括多个放大器。多个放大器中的每一个包括与放大器的输入通信的输入电路和与输入电路通信的启动电路。启动电路被配置为产生启动信号以使能放大器的后续操作。输出电路与放大器的输出以及输入电路和启动电路进行通信。多个放大器的第一和第二放大器的相应输入端与多个放大器的第三放大器的输出端相通。第二放大器的输出与第三放大器的输入端通信。

9. 发明授权

US07454634B1 Power savings apparatus and method for wireless network devices 有权
标题翻译：无线网络设备的省电设备和方法
公开(公告)号：US07454634B1
公开(公告)日：2008-11-18
申请号：US11070481
申请日：2005-03-02
申请人： Timothy Donovan , Shafiq Jamal , Yonghua Song , Chia-Chun Chung , Tam Tran , Lawrence Tse
发明人： Timothy Donovan , Shafiq Jamal , Yonghua Song , Chia-Chun Chung , Tam Tran , Lawrence Tse
IPC分类号： G06F1/32
CPC分类号： H04W52/029 , Y02D70/142 , Y02D70/22
摘要： A wireless network device having active and inactive modes comprises a clock generating module that generates a first clock signal having a first clock rate. A voltage supply module generates a first voltage level and a second voltage level that is less than the first voltage level. A first digital module receives the first clock rate and the first voltage level during the active mode, receives the second voltage level during the inactive mode and does not receive the first clock signal during the inactive mode. A first analog module communicates with the voltage supply module and has reduced current consumption during the inactive mode.
摘要翻译：具有有源和不活动模式的无线网络设备包括产生具有第一时钟速率的第一时钟信号的时钟产生模块。电压供应模块产生小于第一电压电平的第一电压电平和第二电压电平。第一数字模块在活动模式期间接收第一时钟速率和第一电压电平，在非活动模式期间接收第二电压电平，并且在非活动模式期间不接收第一时钟信号。第一模拟模块与电压供应模块通信，并且在非活动模式期间具有减少的电流消耗。

10. 发明授权

US07259600B1 Scalable integrated circuit architecture 有权
标题翻译：可扩展集成电路架构
公开(公告)号：US07259600B1
公开(公告)日：2007-08-21
申请号：US11542978
申请日：2006-10-04
申请人： Yonghua Song
发明人： Yonghua Song
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03L7/0805
摘要： An integrated circuit architecture comprises a phase lock loop (PLL) circuit that includes a feedback circuit that receives a reference signal. A voltage controlled oscillator (VCO) generates an output signal to an input of the feedback circuit. A master transistor has a control terminal, a first terminal, and a second terminal that communicates with the VCO. The feedback circuit compares the output signal of the VCO to the reference signal and outputs a drive signal to the control terminal of the master transistor based on the comparison. N slave transistors have control terminals that communicate with the control terminal of the master transistor, first terminals, and second terminals.
摘要翻译：集成电路架构包括锁相环（PLL）电路，其包括接收参考信号的反馈电路。压控振荡器（VCO）产生到反馈电路的输入端的输出信号。主晶体管具有与VCO通信的控制端子，第一端子和第二端子。反馈电路将VCO的输出信号与参考信号进行比较，并根据比较将驱动信号输出到主晶体管的控制端。 N个从属晶体管具有与主晶体管，第一端子和第二端子的控制端子通信的控制端子。

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