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1. 发明申请

US20090020820A1 CHANNEL-STRESSED SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION 有权
标题翻译：通道应力半导体器件和制造方法
公开(公告)号：US20090020820A1
公开(公告)日：2009-01-22
申请号：US12138502
申请日：2008-06-13
申请人： Hion-suck BAIK , Jong-bong PARK , Jung-yun WON , Hwa-sung RHEE , Byung-seo KIM , Ho LEE , Myung-sun KIM , Ji-hye YI
发明人： Hion-suck BAIK , Jong-bong PARK , Jung-yun WON , Hwa-sung RHEE , Byung-seo KIM , Ho LEE , Myung-sun KIM , Ji-hye YI
IPC分类号： H01L27/088 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device.
摘要翻译：一方面，提供一种制造半导体器件的方法。该方法包括在PMOS器件的外延源极/漏极区域上形成至少一个覆盖层，在包括至少一个覆盖层并且在相邻的NMOS器件上的PMOS器件上形成应力记忆（SM）层，以及处理SM 形成在NMOS和PMOS器件上的层，以在NMOS器件的沟道区域中引起拉伸应力。

2. 发明申请

US20080121992A1 SEMICONDUCTOR DEVICE INCLUDING DIFFUSION BARRIER REGION AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：包括扩展障碍区域的半导体器件及其制造方法
公开(公告)号：US20080121992A1
公开(公告)日：2008-05-29
申请号：US11835551
申请日：2007-08-08
申请人： Ji-hye YI , Hwa-sung RHEE , Tetsuji UENO , Ho LEE , Myung-sun KIM
发明人： Ji-hye YI , Hwa-sung RHEE , Tetsuji UENO , Ho LEE , Myung-sun KIM
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A semiconductor device includes a substrate having an n-type transistor region and a p-type transistor region. The n-type transistor region includes a first gate electrode, first source/drain regions located adjacent to the first gate electrode, a first channel region located between the first source/drain regions, and a first diffusion barrier region located in the first source/drain regions or in both the first channel region and the first source/drain regions. The p-type transistor region includes a second gate electrode, second source/drain regions located adjacent to the second gate electrode, a second channel region located between the second source/drain regions, and a second diffusion barrier region located in the second source/drain regions or in both the second channel region and the second source/drain regions.
摘要翻译：半导体器件包括具有n型晶体管区域和p型晶体管区域的衬底。 n型晶体管区域包括第一栅极电极，位于第一栅极电极附近的第一源极/漏极区域，位于第一源极/漏极区域之间的第一沟道区域和位于第一源极/漏极区域中的第一扩散阻挡区域，漏极区域或者在第一沟道区域和第一源极/漏极区域两者中。 p型晶体管区域包括第二栅极电极，位于第二栅极电极附近的第二源极/漏极区域，位于第二源极/漏极区域之间的第二沟道区域和位于第二源极/漏极区域中的第二扩散阻挡区域，漏极区域或者在第二沟道区域和第二源极/漏极区域中。

3. 发明申请

US20130249016A1 SEMICONDUCTOR DEVICE HAVING ANALOG TRANSISTOR WITH IMPROVED OPERATING AND FLICKER NOISE CHARACTERISTICS AND METHOD OF MAKING SAME 审中-公开
标题翻译：具有改进的操作和闪烁噪声特性的模拟晶体管的半导体器件及其制造方法
公开(公告)号：US20130249016A1
公开(公告)日：2013-09-26
申请号：US13897908
申请日：2013-05-20
申请人： Tetsuji UENO , Hwa-sung RHEE , Ho LEE
发明人： Tetsuji UENO , Hwa-sung RHEE , Ho LEE
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L29/4933 , H01L29/665 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.
摘要翻译：具有改善的晶体管操作和闪烁噪声特性的半导体器件包括衬底，模拟NMOS晶体管和设置在衬底上的压缩应变通道模拟PMOS晶体管。该器件还包括分别覆盖NMOS晶体管和PMOS晶体管的第一蚀刻停止衬垫（ESL）和第二ESL。在500 Hz频率下，NMOS和PMOS晶体管的闪烁噪声功率相对于参考无约束通道模拟NMOS和PMOS晶体管的闪烁噪声功率的相对测量值小于1。

4. 发明申请

US20110233611A1 SEMICONDUCTOR DEVICE HAVING ANALOG TRANSISTOR WITH IMPROVED OPERATING AND FLICKER NOISE CHARACTERISTICS AND METHOD OF MAKING SAME 有权
标题翻译：具有改进的操作和闪烁噪声特性的模拟晶体管的半导体器件及其制造方法
公开(公告)号：US20110233611A1
公开(公告)日：2011-09-29
申请号：US13091327
申请日：2011-04-21
申请人： Tetsuji UENO , Hwa-sung RHEE , Ho LEE
发明人： Tetsuji UENO , Hwa-sung RHEE , Ho LEE
IPC分类号： H01L29/78
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L29/4933 , H01L29/665 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.
摘要翻译：具有改善的晶体管操作和闪烁噪声特性的半导体器件包括衬底，模拟NMOS晶体管和设置在衬底上的压缩应变通道模拟PMOS晶体管。该器件还包括分别覆盖NMOS晶体管和PMOS晶体管的第一蚀刻停止衬垫（ESL）和第二ESL。在500 Hz频率下，NMOS和PMOS晶体管的闪烁噪声功率相对于参考无约束通道模拟NMOS和PMOS晶体管的闪烁噪声功率的相对测量值小于1。

5. 发明申请

US20160284706A1 INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：集成电路装置及其制造方法
公开(公告)号：US20160284706A1
公开(公告)日：2016-09-29
申请号：US15014928
申请日：2016-02-03
申请人： Jae-yup CHUNG , Jong-shik YOON , Hwa-sung RHEE , Hee-don JEONG , Je-Min YOO , Kyu-man CHA , Jong-mil YOUN , Hyun-jo KIM
发明人： Jae-yup CHUNG , Jong-shik YOON , Hwa-sung RHEE , Hee-don JEONG , Je-Min YOO , Kyu-man CHA , Jong-mil YOUN , Hyun-jo KIM
IPC分类号： H01L27/092 , H01L27/02 , H01L29/06 , H01L29/78 , H01L27/088
CPC分类号： H01L27/0924 , H01L21/76229 , H01L21/76232 , H01L21/823821 , H01L21/82385 , H01L21/823878 , H01L27/0207 , H01L27/0886 , H01L29/7846
摘要： An integrated circuit (IC) device includes a fin-type active region formed in a substrate, a step insulation layer on at least one sidewall of the fin-type active region, and a first high-level isolation layer on the at least one sidewall of the fin-type active region. The fin-type active region protrudes from the substrate and extending in a first direction parallel to a main surface of the substrate, includes a channel region having a first conductivity type, and includes the stepped portion. The step insulation layer contacts the stepped portion of the fin-type active region. The step insulation layer is between the first high-level isolation layer and the at least one sidewall of the fin-type active region. The first high-level isolation layer extends in a second direction that is different from the first direction.
摘要翻译：集成电路（IC）装置包括形成在衬底中的翅片型有源区，翅片型有源区的至少一个侧壁上的阶梯绝缘层，以及至少一个侧壁上的第一高电平隔离层的鳍式活性区域。翅片型有源区域从基板突出并且在平行于基板的主表面的第一方向上延伸，包括具有第一导电类型的沟道区域，并且包括台阶部分。台阶绝缘层接触翅片型有源区的台阶部分。台阶绝缘层在第一高电平隔离层和鳍式有源区的至少一个侧壁之间。第一高级隔离层在与第一方向不同的第二方向上延伸。

6. 发明申请

US20160247876A1 Integrated Circuit Devices and Methods of Manufacturing the Same 有权
标题翻译：集成电路器件及其制造方法
公开(公告)号：US20160247876A1
公开(公告)日：2016-08-25
申请号：US14965982
申请日：2015-12-11
申请人： Jae-yup Chung , Yoon-seok LEE , Hyun-jo KIM , Hwa-sung RHEE , Hee-don JEONG , Se-wan PARK , Bo-cheol JEONG
发明人： Jae-yup Chung , Yoon-seok LEE , Hyun-jo KIM , Hwa-sung RHEE , Hee-don JEONG , Se-wan PARK , Bo-cheol JEONG
IPC分类号： H01L29/06 , H01L29/417 , H01L29/10 , H01L29/08 , H01L27/092 , H01L29/78
CPC分类号： H01L21/823481 , H01L21/8232 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/0886 , H01L27/0924 , H01L27/10879 , H01L29/0649 , H01L29/0843 , H01L29/1033 , H01L29/41791 , H01L29/785
摘要： An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalk of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalk of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.
摘要翻译：集成电路器件包括具有不同导电类型沟道区的第一和第二鳍式有源区，覆盖第一鳍式有源区的人行道的第一器件隔离层和覆盖第二鳍的两侧壁的第二器件隔离层型活性区。第一器件隔离层和第二器件隔离层具有不同的堆叠结构。为了制造集成电路器件，覆盖第一鳍式有源区的两个侧壁的第一器件隔离层和覆盖第二鳍式有源区的人行道的第二器件隔离层在第一鳍式有源区并形成第二鳍型有源区。第一器件隔离层和第二器件隔离层形成为具有不同的堆叠结构。

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