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1. 发明申请

US20090020820A1 CHANNEL-STRESSED SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION 有权
标题翻译：通道应力半导体器件和制造方法
公开(公告)号：US20090020820A1
公开(公告)日：2009-01-22
申请号：US12138502
申请日：2008-06-13
申请人： Hion-suck BAIK , Jong-bong PARK , Jung-yun WON , Hwa-sung RHEE , Byung-seo KIM , Ho LEE , Myung-sun KIM , Ji-hye YI
发明人： Hion-suck BAIK , Jong-bong PARK , Jung-yun WON , Hwa-sung RHEE , Byung-seo KIM , Ho LEE , Myung-sun KIM , Ji-hye YI
IPC分类号： H01L27/088 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device.
摘要翻译：一方面，提供一种制造半导体器件的方法。该方法包括在PMOS器件的外延源极/漏极区域上形成至少一个覆盖层，在包括至少一个覆盖层并且在相邻的NMOS器件上的PMOS器件上形成应力记忆（SM）层，以及处理SM 形成在NMOS和PMOS器件上的层，以在NMOS器件的沟道区域中引起拉伸应力。

2. 发明申请

US20080105899A1 SEMICONDUCTOR DEVICE WITH EPITAXIALLY GROWN LAYER AND FABRICATION METHOD 审中-公开
标题翻译：具有外延层的半导体器件和制造方法
公开(公告)号：US20080105899A1
公开(公告)日：2008-05-08
申请号：US11858288
申请日：2007-09-20
申请人： Young-pil KIM , Jin-bum KIM , Jun-ho LEE , Jung-yun WON , In-sun JUNG
发明人： Young-pil KIM , Jin-bum KIM , Jun-ho LEE , Jung-yun WON , In-sun JUNG
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L21/26513 , H01L29/66575 , H01L29/66628 , H01L29/78
摘要： A fabrication method and a related semiconductor device are disclosed. The method includes; forming a gate structure on a semiconductor substrate, the gate structure comprising a stacked combination a gate dielectric pattern, a gate, a capping layer pattern and an epitaxial blocking layer pattern, forming sidewall spacers on the gate structure covering at least sidewall portions of the gate dielectric pattern, the gate, and the capping layer pattern, wherein the epitaxial blocking layer pattern is exposed on a top surface of the gate structure, forming an elevated epitaxial layer on the semiconductor substrate outside the gate structure using a selective epitaxial growth process, and forming elevated source/drain regions by applying an ion implantation process to the semiconductor substrate following formation of the elevated epitaxial layer, wherein the epitaxial blocking layer is a nitrogen enhanced layer relative to the capping layer pattern.
摘要翻译：公开了一种制造方法和相关的半导体器件。该方法包括：在半导体衬底上形成栅极结构，所述栅极结构包括层叠组合栅极电介质图案，栅极，覆盖层图案和外延阻挡层图案，在所述栅极结构上形成至少覆盖所述栅极的侧壁部分的侧壁间隔物电介质图案，栅极和覆盖层图案，其中外延阻挡层图案暴露在栅极结构的顶表面上，使用选择性外延生长工艺在栅极结构外部的半导体衬底上形成升高的外延层，以及通过在形成升高的外延层之后对半导体衬底施加离子注入工艺来形成升高的源/漏区，其中外延阻挡层相对于覆盖层图案是氮增强层。

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